lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Wed, 16 Dec 2020 06:12:30 +0000 From: Yash Shah <yash.shah@...nfive.com> To: Bin Meng <bmeng.cn@...il.com> CC: "linux-spi@...r.kernel.org" <linux-spi@...r.kernel.org>, "linux-serial@...r.kernel.org" <linux-serial@...r.kernel.org>, "linux-pwm@...r.kernel.org" <linux-pwm@...r.kernel.org>, "linux-i2c@...r.kernel.org" <linux-i2c@...r.kernel.org>, linux-kernel <linux-kernel@...r.kernel.org>, linux-riscv <linux-riscv@...ts.infradead.org>, devicetree <devicetree@...r.kernel.org>, "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>, "broonie@...nel.org" <broonie@...nel.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Albert Ou <aou@...s.berkeley.edu>, "lee.jones@...aro.org" <lee.jones@...aro.org>, "u.kleine-koenig@...gutronix.de" <u.kleine-koenig@...gutronix.de>, Thierry Reding <thierry.reding@...il.com>, "andrew@...n.ch" <andrew@...n.ch>, Peter Korsgaard <peter@...sgaard.com>, "Paul Walmsley ( Sifive)" <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Rob Herring <robh+dt@...nel.org>, Bartosz Golaszewski <bgolaszewski@...libre.com>, Linus Walleij <linus.walleij@...aro.org> Subject: RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC > -----Original Message----- > From: Bin Meng <bmeng.cn@...il.com> > Sent: 16 December 2020 11:36 > To: Yash Shah <yash.shah@...nfive.com> > Cc: linux-spi@...r.kernel.org; linux-serial@...r.kernel.org; linux- > pwm@...r.kernel.org; linux-i2c@...r.kernel.org; linux-kernel <linux- > kernel@...r.kernel.org>; linux-riscv <linux-riscv@...ts.infradead.org>; > devicetree <devicetree@...r.kernel.org>; open list:GPIO SUBSYSTEM <linux- > gpio@...r.kernel.org>; broonie@...nel.org; Greg Kroah-Hartman > <gregkh@...uxfoundation.org>; Albert Ou <aou@...s.berkeley.edu>; > lee.jones@...aro.org; u.kleine-koenig@...gutronix.de; Thierry Reding > <thierry.reding@...il.com>; andrew@...n.ch; Peter Korsgaard > <peter@...sgaard.com>; Paul Walmsley ( Sifive) > <paul.walmsley@...ive.com>; Palmer Dabbelt <palmer@...belt.com>; Rob > Herring <robh+dt@...nel.org>; Bartosz Golaszewski > <bgolaszewski@...libre.com>; Linus Walleij <linus.walleij@...aro.org> > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740- > C000 SoC > > [External Email] Do not click links or attachments unless you recognize the > sender and know the content is safe > > Hi Yash, > > On Wed, Dec 16, 2020 at 1:24 PM Yash Shah <yash.shah@...nfive.com> > wrote: > > > > > -----Original Message----- > > > From: Bin Meng <bmeng.cn@...il.com> > > > Sent: 10 December 2020 19:05 > > > To: Yash Shah <yash.shah@...nfive.com> > > > Cc: linux-spi@...r.kernel.org; linux-serial@...r.kernel.org; linux- > > > pwm@...r.kernel.org; linux-i2c@...r.kernel.org; linux-kernel <linux- > > > kernel@...r.kernel.org>; linux-riscv > > > <linux-riscv@...ts.infradead.org>; > > > devicetree <devicetree@...r.kernel.org>; open list:GPIO SUBSYSTEM > > > <linux- gpio@...r.kernel.org>; broonie@...nel.org; Greg > > > Kroah-Hartman <gregkh@...uxfoundation.org>; Albert Ou > > > <aou@...s.berkeley.edu>; lee.jones@...aro.org; > > > u.kleine-koenig@...gutronix.de; Thierry Reding > > > <thierry.reding@...il.com>; andrew@...n.ch; Peter Korsgaard > > > <peter@...sgaard.com>; Paul Walmsley ( Sifive) > > > <paul.walmsley@...ive.com>; Palmer Dabbelt <palmer@...belt.com>; > Rob > > > Herring <robh+dt@...nel.org>; Bartosz Golaszewski > > > <bgolaszewski@...libre.com>; Linus Walleij > > > <linus.walleij@...aro.org> > > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the > > > SiFive FU740- > > > C000 SoC > > > > > > [External Email] Do not click links or attachments unless you > > > recognize the sender and know the content is safe > > > > > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah <yash.shah@...ive.com> > wrote: > > > > > > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is > > > > built > > > > > > FU740-C000 Soc > > > > > > > around the SiFIve U7 Core Complex and a TileLink interconnect. > > > > > > > > This file is expected to grow as more device drivers are added to > > > > the kernel. > > > > > > > > Signed-off-by: Yash Shah <yash.shah@...ive.com> > > > > --- > > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293 > > > > +++++++++++++++++++++++++++++ > > > > 1 file changed, 293 insertions(+) create mode 100644 > > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > > > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > new file mode 100644 > > > > index 0000000..eeb4f8c3 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi > > > > @@ -0,0 +1,293 @@ > > > > ... > > > > > > + plic0: interrupt-controller@...0000 { > > > > + #interrupt-cells = <1>; > > > > + #address-cells = <0>; > > > > + compatible = "sifive,fu540-c000-plic", > > > > + "sifive,plic-1.0.0"; > > > > > > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"? > > > > That's because it is not required. There won't be any difference in driver > code for FU740 plic. > > Are there any driver changes for the drivers that have an updated > fu640-c000-* bindings? I don't see them in the linux-riscv list. Yes, they will be posted soon. - Yash > > > > > ... > > > > > > + eth0: ethernet@...90000 { > > > > + compatible = "sifive,fu540-c000-gem"; > > > > > > "sifive,fu740-c000-gem"? > > > > > > > Same reason as above. > > > > Thanks for your review. > > Regards, > Bin
Powered by blists - more mailing lists