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Date:   Wed, 16 Dec 2020 13:56:23 +0300
From:   "Kirill A. Shutemov" <kirill@...temov.name>
To:     Lorenzo Stoakes <lstoakes@...il.com>
Cc:     Dave Hansen <dave.hansen@...ux.intel.com>,
        Andy Lutomirski <luto@...nel.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        x86@...nel.org, "H . Peter Anvin" <hpa@...or.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] x86/mm: increase pgt_buf size for 5-level page tables

On Tue, Dec 15, 2020 at 08:56:41PM +0000, Lorenzo Stoakes wrote:
> pgt_buf is used to allocate page tables on initial direct page mapping
> bootstrapping us into being able to allocate these before the direct
> mapping makes further pages available.
> 
> INIT_PGD_PAGE_COUNT is set to 6 pages (doubled for KASLR) - 3 (PUD, PMD,
> PTE) for the 1 MiB ISA mapping and 3 more for the first direct mapping
> assignment in each case providing 2 MiB of address space.
> 
> This has not been updated for 5-level page tables which additionally has a
> P4D page table level above PUD.
> 
> In most instances this will not have a material impact as the first 4 page
> levels allocated for the ISA mapping will provide sufficient address space
> to encompass all further address mappings. If the first direct mapping is
> within 512 GiB of the ISA mapping we need only add a PMD and PTE in the
> instance where we are using 4 KiB page tables (e.g. CONFIG_DEBUG_PAGEALLOC
> is enabled) and only a PMD if we can use 2 MiB pages (the first allocation
> is limited to PMD_SIZE so we can't use a GiB page there).
> 
> However if we have more than 512 GiB of RAM and are allocating 4 KiB page
> size we require 3 further page tables and if we have more than 256 TiB of
> RAM at 4 KiB or 2 MiB page size we require a further 3 or 4 page tables
> respectively.
> 
> This patch updates INIT_PGD_PAGE_COUNT to reflect this.
> 
> Signed-off-by: Lorenzo Stoakes <lstoakes@...il.com>

Acked-by: Kirill A. Shutemov <kirill.shutemov@...ux.intel.com>

-- 
 Kirill A. Shutemov

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