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Date: Wed, 16 Dec 2020 19:36:30 +0800
From: Yong Wu <yong.wu@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>
CC: Krzysztof Kozlowski <krzk@...nel.org>,
Joerg Roedel <joro@...tes.org>,
Robin Murphy <robin.murphy@....com>,
Rob Herring <robh+dt@...nel.org>,
Tomasz Figa <tfiga@...gle.com>,
<linux-mediatek@...ts.infradead.org>,
<srv_heupstream@...iatek.com>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<iommu@...ts.linux-foundation.org>, <weiyi.lu@...iatek.com>,
<yong.wu@...iatek.com>, <youlin.pei@...iatek.com>,
Nicolas Boichat <drinkcat@...omium.org>,
<anan.sun@...iatek.com>, <yi.kuo@...iatek.com>,
<chao.hao@...iatek.com>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: [PATCH] arm64: dts: mt8192: add m4u and smi nodes
Add mt8192 IOMMU and smi larb/common nodes.
Signed-off-by: Yong Wu <yong.wu@...iatek.com>
---
This patch base on:
1. mt8192 dts base which is in the linux-next now.
https://lore.kernel.org/linux-mediatek/20201030092207.26488-2-seiya.wang@mediatek.com/
2. clock nodes and definitions:
https://lore.kernel.org/linux-mediatek/1604887429-29445-1-git-send-email-weiyi.lu@mediatek.com/
3. PM definitions:
https://patchwork.kernel.org/project/linux-mediatek/patch/20201030113622.201188-15-enric.balletbo@collabora.com/
4. PM nodes:
https://lore.kernel.org/linux-mediatek/1605782884-19741-1-git-send-email-weiyi.lu@mediatek.com/
5. iommu ports defintions:
https://lore.kernel.org/linux-iommu/20201209080102.26626-1-yong.wu@mediatek.com/T/#t
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 193 +++++++++++++++++++++++
1 file changed, 193 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index a315568fcd9a..b84585de5ca8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8192-larb-port.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/power/mt8192-power.h>
@@ -807,24 +808,116 @@
#clock-cells = <1>;
};
+ smi_common: smi@...02000 {
+ compatible = "mediatek,mt8192-smi-common";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_GALS>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb0: larb@...03000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,larb-id = <0>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_INFRA>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb1: larb@...04000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,larb-id = <1>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_INFRA>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ iommu0: m4u@...1d000 {
+ compatible = "mediatek,mt8192-m4u";
+ reg = <0 0x1401d000 0 0x1000>;
+ mediatek,larbs = <&larb0 &larb1 &larb2
+ &larb4 &larb5 &larb7
+ &larb9 &larb11 &larb13
+ &larb14 &larb16 &larb17
+ &larb18 &larb19 &larb20>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "bclk";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ #iommu-cells = <1>;
+ };
+
imgsys: syscon@...20000 {
compatible = "mediatek,mt8192-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
+ larb9: larb@...2e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1502e000 0 0x1000>;
+ mediatek,larb-id = <9>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
+ };
+
imgsys2: syscon@...20000 {
compatible = "mediatek,mt8192-imgsys2", "syscon";
reg = <0 0x15820000 0 0x1000>;
#clock-cells = <1>;
};
+ larb11: larb@...2e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1582e000 0 0x1000>;
+ mediatek,larb-id = <11>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys2 CLK_IMG2_LARB11>,
+ <&imgsys2 CLK_IMG2_LARB11>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
+ };
+
+ larb5: larb@...0d000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1600d000 0 0x1000>;
+ mediatek,larb-id = <5>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
vdecsys_soc: syscon@...0f000 {
compatible = "mediatek,mt8192-vdecsys_soc", "syscon";
reg = <0 0x1600f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb4: larb@...2e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1602e000 0 0x1000>;
+ mediatek,larb-id = <4>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
+ <&vdecsys CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+
vdecsys: syscon@...2f000 {
compatible = "mediatek,mt8192-vdecsys", "syscon";
reg = <0 0x1602f000 0 0x1000>;
@@ -837,12 +930,79 @@
#clock-cells = <1>;
};
+ larb7: larb@...10000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x17010000 0 0x1000>;
+ mediatek,larb-id = <7>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vencsys CLK_VENC_SET0_LARB>,
+ <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+ };
+
camsys: syscon@...00000 {
compatible = "mediatek,mt8192-camsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb13: larb@...01000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a001000 0 0x1000>;
+ mediatek,larb-id = <13>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB13>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb14: larb@...02000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a002000 0 0x1000>;
+ mediatek,larb-id = <14>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB14>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb16: larb@...0f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a00f000 0 0x1000>;
+ mediatek,larb-id = <16>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "apb", "smi";
+ mediatek,smi-id = <16>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb17: larb@...10000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a010000 0 0x1000>;
+ mediatek,larb-id = <17>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
+ <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
+ };
+
+ larb18: larb@...11000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a011000 0 0x1000>;
+ mediatek,larb-id = <18>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
+ <&camsys_rawc CLK_CAM_RAWC_CAM>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
+ };
+
camsys_rawa: syscon@...4f000 {
compatible = "mediatek,mt8192-camsys_rawa", "syscon";
reg = <0 0x1a04f000 0 0x1000>;
@@ -867,10 +1027,43 @@
#clock-cells = <1>;
};
+ larb20: larb@...0f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b00f000 0 0x1000>;
+ mediatek,larb-id = <20>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB20>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
+ larb19: larb@...0f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b10f000 0 0x1000>;
+ mediatek,larb-id = <19>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB19>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
mdpsys: syscon@...00000 {
compatible = "mediatek,mt8192-mdpsys", "syscon";
reg = <0 0x1f000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ larb2: larb@...02000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1f002000 0 0x1000>;
+ mediatek,larb-id = <2>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mdpsys CLK_MDP_SMI0>,
+ <&mdpsys CLK_MDP_SMI0>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
+ };
};
};
--
2.18.0
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