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Date:   Wed, 16 Dec 2020 18:01:11 +0000
From:   Mike Leach <mike.leach@...aro.org>
To:     Suzuki K Poulose <suzuki.poulose@....com>
Cc:     linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Mathieu Poirier <mathieu.poirier@...aro.org>,
        Leo Yan <leo.yan@...aro.org>,
        Jonathan Zhou <jonathan.zhouwen@...wei.com>
Subject: Re: [PATCH v5 18/25] coresight: etm4x: Expose trcdevarch via trcidr

Hi Suzuki

On Mon, 14 Dec 2020 at 17:38, Suzuki K Poulose <suzuki.poulose@....com> wrote:
>
> Expose the TRCDEVARCH register via the sysfs for component
> detection. Given that the TRCIDR1 may not completely identify
> the ETM component and instead need to use TRCDEVARCH, expose
> this via sysfs for tools to use it for identification.
>
> Cc: Mike Leach <mike.leach@...aro.org>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@...aro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@....com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 009818675928..277fd5bff811 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -2395,6 +2395,7 @@ coresight_etm4x_cross_read(trcidr10, TRCIDR10);
>  coresight_etm4x_cross_read(trcidr11, TRCIDR11);
>  coresight_etm4x_cross_read(trcidr12, TRCIDR12);
>  coresight_etm4x_cross_read(trcidr13, TRCIDR13);
> +coresight_etm4x_cross_read(trcdevarch, TRCDEVARCH);
>
>  static struct attribute *coresight_etmv4_trcidr_attrs[] = {
>         &dev_attr_trcidr0.attr,
> @@ -2410,6 +2411,7 @@ static struct attribute *coresight_etmv4_trcidr_attrs[] = {
>         &dev_attr_trcidr11.attr,
>         &dev_attr_trcidr12.attr,
>         &dev_attr_trcidr13.attr,
> +       &dev_attr_trcdevarch.attr,
>         NULL,
>  };
>

It makes far more sense for this to appear in the 'mgmt' group, per
the grouping in the Coresight spec. This would place it alongside the
other CoreSight management registers, including DEVID, and DEVTYPE
which is used with DEVARCH in the CoreSight UCI, . This is also
consistent with the CTI which places all three of these registers in
the 'mgmt' section.

Regards

Mike


> --
> 2.24.1
>


-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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