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Message-ID: <160815009047.1580929.7758511273578717067@swboyd.mtv.corp.google.com>
Date: Wed, 16 Dec 2020 12:21:30 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Zong Li <zong.li@...ive.com>, aou@...s.berkeley.edu,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, mturquette@...libre.com,
palmer@...belt.com, paul.walmsley@...ive.com,
pragnesh.patel@...nfive.com, schwab@...ux-m68k.org,
yash.shah@...ive.com
Cc: Zong Li <zong.li@...ive.com>,
Pragnesh Patel <pragnesh.patel@...ive.com>
Subject: Re: [PATCH v7 4/5] clk: sifive: Fix the wrong bit field shift
Quoting Zong Li (2020-12-09 01:49:15)
> The clk enable bit should be 31 instead of 24.
>
> Signed-off-by: Zong Li <zong.li@...ive.com>
> Reported-by: Pragnesh Patel <pragnesh.patel@...ive.com>
> ---
Applied to clk-next
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