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Date: Thu, 17 Dec 2020 13:48:39 +0530 From: Srinivasa Rao Mandadapu <srivasam@...eaurora.org> To: Mark Brown <broonie@...nel.org> Cc: agross@...nel.org, bjorn.andersson@...aro.org, lgirdwood@...il.com, robh+dt@...nel.org, plai@...eaurora.org, bgoswami@...eaurora.org, perex@...ex.cz, tiwai@...e.com, srinivas.kandagatla@...aro.org, rohitkr@...eaurora.org, linux-arm-msm@...r.kernel.org, alsa-devel@...a-project.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, V Sujith Kumar Reddy <vsujithk@...eaurora.org> Subject: Re: [PATCH v4 1/2] Partially revert ASoC: qcom: Fix enabling BCLK and LRCLK in LPAIF invalid state Thanks Mark for your Time!!! On 12/14/2020 11:20 PM, Mark Brown wrote: > On Mon, Dec 14, 2020 at 06:13:22PM +0530, Srinivasa Rao Mandadapu wrote: >> On 12/1/2020 11:21 PM, Mark Brown wrote: >>>> Later from review comments by Srinivas kandagatla, I got to know >>>> >>>> about regcache sync APIs, which can be used to sync cache after resume and >>>> >>>> HW registers can be updated with original values. With that playback can be >>>> continued. >>>> So is the reason, I am reverting partial changes in the commit b1824968221c. >>> I don't understand why a fix for the register cache not being in sync >>> with the hardware doesn't involve syncing the register cache with the >>> hardware. >> I am sorry I couldn't understand your point. Could you please elaborate your >> query? > Your changelog talks about syncing the cache but neither the driver nor > your change actually does that. Okay. Now I posted v6 patch (https://lore.kernel.org/patchwork/patch/1354638/) with subject lines explaining actual changes. could you please check the same. -- Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
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