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Message-Id: <20201217180638.22748-1-digetx@gmail.com>
Date: Thu, 17 Dec 2020 21:05:50 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Mark Brown <broonie@...nel.org>,
Liam Girdwood <lgirdwood@...il.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Peter Geis <pgwipeout@...il.com>,
Nicolas Chauvet <kwizart@...il.com>,
Krzysztof Kozlowski <krzk@...nel.org>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Kevin Hilman <khilman@...nel.org>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Viresh Kumar <vireshk@...nel.org>,
Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>
Cc: devel@...verdev.osuosl.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-media@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: [PATCH v2 00/48] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs
Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
power consumption and heating of the Tegra chips. Tegra SoC has multiple
hardware units which belong to a core power domain of the SoC and share
the core voltage. The voltage must be selected in accordance to a minimum
requirement of every core hardware unit.
The minimum core voltage requirement depends on:
1. Clock enable state of a hardware unit.
2. Clock frequency.
3. Unit's internal idling/active state.
This series is tested on Acer A500 (T20), AC100 (T20), Nexus 7 (T30),
Ouya (T30), TK1 (T124) and some others. I also added voltage scaling to
the Ventana (T20) and Cardhu (T30) boards which are tested by NVIDIA's CI
farm. Tegra30 is now couple degrees cooler on Nexus 7 and stays cool on
Ouya (instead of becoming burning hot) while system is idling. It should
be possible to improve this further by implementing a more advanced power
management features for the kernel drivers.
The DVFS support is opt-in for all boards, meaning that older DTBs will
continue to work like they did it before this series. It should be possible
to easily add the core voltage scaling support for Tegra114+ SoCs based on
this grounding work later on, if anyone will want to implement it.
Changelog:
v2: - Replaced Core voltage regulator with a Core power domain. The voltage
control is now done using GENPD API. This was suggested by Ulf Hansson.
- Added basic runtime PM and GENPD support to 2d, 3d, host1x and clk
drivers.
- Added new core-power-domain and clk-device drivers. Some high-freq
PLLs and clocks require a higher minimum core voltage and the new
clk-device driver manages the voltage for these clocks based on
the clock state.
- Moved voltage scaling entirely to the new clk-device driver for devices
which don't require advanced power management, like PWM for example.
- Added devm_tegra_core_dev_init_opp_table() common helper which sets up
OPP table for Tegra drivers.
- Added resource-managed version for OPP API functions, as it was
discussed previously in the comments to v1.
- Added new APIs, features and fixed various bugs related to voltage
scaling and power management done via GENPD API.
Dmitry Osipenko (48):
dt-bindings: memory: tegra20: emc: Replace core regulator with power
domain
dt-bindings: memory: tegra30: emc: Replace core regulator with power
domain
dt-bindings: memory: tegra124: emc: Replace core regulator with power
domain
dt-bindings: host1x: Document OPP and power domain properties
media: dt: bindings: tegra-vde: Document OPP and power domain
properties
dt-bindings: clock: tegra: Document clocks sub-node
dt-bindings: arm: tegra: Add binding for core power domain
regulator: Make regulator_sync_voltage() usable by coupled regulators
opp: Add dev_pm_opp_sync_regulators()
opp: Add dev_pm_opp_set_voltage()
opp: Add dev_pm_opp_find_level_ceil()
opp: Add dev_pm_opp_get_required_pstate()
opp: Add resource-managed versions of OPP API functions
opp: Filter out OPPs based on availability of a required-OPP
opp: Support set_opp() customization without requiring to use
regulators
opp: Handle missing OPP table in dev_pm_opp_xlate_performance_state()
opp: Correct debug message in _opp_add_static_v2()
opp: Print OPP level in debug message of _opp_add_static_v2()
opp: Fix adding OPP entries in a wrong order if rate is unavailable
PM: domains: Make set_performance_state() callback optional
PM: domains: Add "performance" column to debug summary
soc/tegra: pmc: Fix imbalanced clock disabling in error code path
soc/tegra: pmc: Pulse resets after removing power clamp
soc/tegra: pmc: Ensure that clock rates aren't too high
soc/tegra: pmc: Print out domain name when reset fails to acquire
soc/tegra: Add devm_tegra_core_dev_init_opp_table()
soc/tegra: Add CONFIG_SOC_TEGRA_COMMON and select PM_OPP by default
soc/tegra: Introduce core power domain driver
soc/tegra: pmc: Link domains to the parent Core domain
soc/tegra: regulators: Fix locking up when voltage-spread is out of
range
soc/tegra: regulators: Support Core domain state syncing
clk: tegra: Support runtime PM, power domain and OPP
gpu: host1x: Add host1x_channel_stop()
gpu: host1x: Support power management
drm/tegra: dc: Support OPP and SoC core voltage scaling
drm/tegra: gr2d: Correct swapped device-tree compatibles
drm/tegra: gr2d: Support OPP and power management
drm/tegra: g3d: Support OPP and power management
drm/tegra: vic: Stop channel before suspending
media: staging: tegra-vde: Support OPP and generic power domain
memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table()
memory: tegra30-emc: Use devm_tegra_core_dev_init_opp_table()
ARM: tegra: Add OPP tables and power domains to Tegra20 device-tree
ARM: tegra: Add OPP tables and power domains to Tegra30 device-tree
ARM: tegra: acer-a500: Enable core voltage scaling
ARM: tegra: ventana: Enable core voltage scaling
ARM: tegra: ventana: Support CPU voltage scaling and thermal
throttling
ARM: tegra: cardhu: Support CPU voltage scaling and thermal throttling
.../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 +
.../bindings/clock/nvidia,tegra20-car.txt | 26 +
.../bindings/clock/nvidia,tegra30-car.txt | 26 +
.../display/tegra/nvidia,tegra20-host1x.txt | 49 +
.../bindings/media/nvidia,tegra-vde.txt | 12 +
.../nvidia,tegra124-emc.yaml | 6 +-
.../memory-controllers/nvidia,tegra20-emc.txt | 4 +-
.../nvidia,tegra30-emc.yaml | 6 +-
.../boot/dts/tegra20-acer-a500-picasso.dts | 8 +-
arch/arm/boot/dts/tegra20-colibri.dtsi | 6 +-
arch/arm/boot/dts/tegra20-harmony.dts | 6 +-
arch/arm/boot/dts/tegra20-paz00.dts | 46 +-
.../arm/boot/dts/tegra20-peripherals-opp.dtsi | 941 +++++++++++
arch/arm/boot/dts/tegra20-seaboard.dts | 6 +-
arch/arm/boot/dts/tegra20-tamonten.dtsi | 6 +-
arch/arm/boot/dts/tegra20-trimslice.dts | 12 +
arch/arm/boot/dts/tegra20-ventana.dts | 78 +-
arch/arm/boot/dts/tegra20.dtsi | 220 +++
.../tegra30-asus-nexus7-grouper-common.dtsi | 4 +
arch/arm/boot/dts/tegra30-beaver.dts | 4 +
arch/arm/boot/dts/tegra30-cardhu.dtsi | 81 +-
arch/arm/boot/dts/tegra30-colibri.dtsi | 20 +-
arch/arm/boot/dts/tegra30-ouya.dts | 4 +
.../arm/boot/dts/tegra30-peripherals-opp.dtsi | 1412 +++++++++++++++++
arch/arm/boot/dts/tegra30.dtsi | 358 +++++
drivers/base/power/domain.c | 33 +-
drivers/clk/tegra/Makefile | 1 +
drivers/clk/tegra/clk-device.c | 222 +++
drivers/clk/tegra/clk-divider.c | 2 +-
drivers/clk/tegra/clk-periph-gate.c | 2 +-
drivers/clk/tegra/clk-periph.c | 2 +-
drivers/clk/tegra/clk-pll.c | 2 +-
drivers/clk/tegra/clk-super.c | 4 +-
drivers/clk/tegra/clk-tegra-periph.c | 140 +-
drivers/clk/tegra/clk-tegra114.c | 1 +
drivers/clk/tegra/clk-tegra124.c | 1 +
drivers/clk/tegra/clk-tegra20-emc.c | 2 +-
drivers/clk/tegra/clk-tegra20.c | 123 +-
drivers/clk/tegra/clk-tegra210.c | 1 +
drivers/clk/tegra/clk-tegra30.c | 133 +-
drivers/clk/tegra/clk.c | 89 ++
drivers/clk/tegra/clk.h | 7 +
drivers/gpu/drm/tegra/dc.c | 66 +-
drivers/gpu/drm/tegra/gr2d.c | 77 +-
drivers/gpu/drm/tegra/gr3d.c | 264 ++-
drivers/gpu/drm/tegra/vic.c | 15 +
drivers/gpu/host1x/channel.c | 8 +
drivers/gpu/host1x/dev.c | 102 +-
drivers/memory/tegra/tegra20-emc.c | 57 +-
drivers/memory/tegra/tegra30-emc.c | 57 +-
drivers/opp/core.c | 390 ++++-
drivers/opp/of.c | 34 +-
drivers/opp/opp.h | 2 +-
drivers/regulator/core.c | 6 +
drivers/soc/tegra/Kconfig | 19 +
drivers/soc/tegra/Makefile | 1 +
drivers/soc/tegra/common.c | 137 ++
drivers/soc/tegra/core-power-domain.c | 125 ++
drivers/soc/tegra/pmc.c | 122 +-
drivers/soc/tegra/regulators-tegra20.c | 19 +-
drivers/soc/tegra/regulators-tegra30.c | 20 +-
drivers/staging/media/tegra-vde/vde.c | 63 +-
include/linux/host1x.h | 1 +
include/linux/pm_opp.h | 81 +
include/soc/tegra/common.h | 41 +
65 files changed, 5458 insertions(+), 403 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml
create mode 100644 drivers/clk/tegra/clk-device.c
create mode 100644 drivers/soc/tegra/core-power-domain.c
--
2.29.2
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