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Message-Id: <20201217180638.22748-7-digetx@gmail.com>
Date: Thu, 17 Dec 2020 21:05:56 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Mark Brown <broonie@...nel.org>,
Liam Girdwood <lgirdwood@...il.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Peter Geis <pgwipeout@...il.com>,
Nicolas Chauvet <kwizart@...il.com>,
Krzysztof Kozlowski <krzk@...nel.org>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Kevin Hilman <khilman@...nel.org>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Viresh Kumar <vireshk@...nel.org>,
Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>
Cc: devel@...verdev.osuosl.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-media@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-clk@...r.kernel.org
Subject: [PATCH v2 06/48] dt-bindings: clock: tegra: Document clocks sub-node
Document "clocks" sub-node which describes Tegra SoC clocks that require
a higher voltage of the core power domain in order to operate properly on
a higher rates.
Signed-off-by: Dmitry Osipenko <digetx@...il.com>
---
.../bindings/clock/nvidia,tegra20-car.txt | 26 +++++++++++++++++++
.../bindings/clock/nvidia,tegra30-car.txt | 26 +++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index 6c5901b503d0..353354477785 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -19,6 +19,16 @@ Required properties :
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
+Optional child sub-node "clocks" should contain nodes matching the clocks
+on the Tegra SoC. Refer to Tegra TRM for mode details on the clock nodes.
+
+Required properties :
+- compatible : Should be "nvidia,tegra20-clock".
+- operating-points-v2: See ../bindings/opp/opp.txt for details.
+- clocks : Should contain clock which corresponds to the node.
+- power-domains: Phandle to a power domain node as described by generic
+ PM domain bindings.
+
Example SoC include file:
/ {
@@ -27,6 +37,22 @@ Example SoC include file:
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+
+ clocks {
+ hdmi {
+ compatible = "nvidia,tegra20-clock";
+ operating-points-v2 = <&hdmi_opp_table>;
+ clocks = <&tegra_car TEGRA20_CLK_HDMI>;
+ power-domains = <&domain>;
+ };
+
+ pll_m {
+ compatible = "nvidia,tegra20-clock";
+ operating-points-v2 = <&pll_m_opp_table>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_M>;
+ power-domains = <&domain>;
+ };
+ };
};
usb@...04000 {
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
index 63618cde12df..bc7bbdaa9d3f 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt
@@ -19,6 +19,16 @@ Required properties :
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
+Optional child sub-node "clocks" should contain nodes matching the clocks
+on the Tegra SoC. Refer to Tegra TRM for mode details on the clock nodes.
+
+Required properties :
+- compatible : Should be "nvidia,tegra30-clock".
+- operating-points-v2: See ../bindings/opp/opp.txt for details.
+- clocks : Should contain clock which corresponds to the node.
+- power-domains: Phandle to a power domain node as described by generic
+ PM domain bindings.
+
Example SoC include file:
/ {
@@ -31,6 +41,22 @@ Example SoC include file:
usb@...04000 {
clocks = <&tegra_car TEGRA30_CLK_USB2>;
+
+ clocks {
+ hdmi {
+ compatible = "nvidia,tegra30-clock";
+ operating-points-v2 = <&hdmi_opp_table>;
+ clocks = <&tegra_car TEGRA30_CLK_HDMI>;
+ power-domains = <&domain>;
+ };
+
+ pll_m {
+ compatible = "nvidia,tegra30-clock";
+ operating-points-v2 = <&pll_m_opp_table>;
+ clocks = <&tegra_car TEGRA30_CLK_PLL_M>;
+ power-domains = <&domain>;
+ };
+ };
};
};
--
2.29.2
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