lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20201218092106.skwej2g6bk3oksbb@ti.com>
Date:   Fri, 18 Dec 2020 14:51:08 +0530
From:   Pratyush Yadav <p.yadav@...com>
To:     Sowjanya Komatineni <skomatineni@...dia.com>
CC:     <thierry.reding@...il.com>, <jonathanh@...dia.com>,
        <broonie@...nel.org>, <robh+dt@...nel.org>, <lukas@...ner.de>,
        <bbrezillon@...nel.org>, <tudor.ambarus@...rochip.com>,
        <linux-spi@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH v4 5/9] spi: spi-mem: Mark dummy transfers by setting
 dummy_data bit

Hi Sowjanya,

On 17/12/20 12:28PM, Sowjanya Komatineni wrote:
> This patch marks dummy transfer by setting dummy_data bit to 1.
> 
> Controllers supporting dummy transfer by hardware use this bit field
> to skip software transfer of dummy bytes and use hardware dummy bytes
> transfer.

What is the benefit you get from this change? You add complexity in 
spi-mem and the controller driver, so that must come with some benefits. 
Here I don't see any. The transfer will certainly take the same amount 
of time because the number or period of the dummy cycles has not 
changed. So why is this needed?
 
> Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
> ---
>  drivers/spi/spi-mem.c   | 1 +
>  include/linux/spi/spi.h | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
> index f3a3f19..c64371c 100644
> --- a/drivers/spi/spi-mem.c
> +++ b/drivers/spi/spi-mem.c
> @@ -354,6 +354,7 @@ int spi_mem_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
>  		xfers[xferpos].tx_buf = tmpbuf + op->addr.nbytes + 1;
>  		xfers[xferpos].len = op->dummy.nbytes;
>  		xfers[xferpos].tx_nbits = op->dummy.buswidth;
> +		xfers[xferpos].dummy_data = 1;
>  		spi_message_add_tail(&xfers[xferpos], &msg);
>  		xferpos++;
>  		totalxferlen += op->dummy.nbytes;
> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> index aa09fdc..708f2f5 100644
> --- a/include/linux/spi/spi.h
> +++ b/include/linux/spi/spi.h
> @@ -827,6 +827,7 @@ extern void spi_res_release(struct spi_controller *ctlr,
>   *      transfer. If 0 the default (from @spi_device) is used.
>   * @bits_per_word: select a bits_per_word other than the device default
>   *      for this transfer. If 0 the default (from @spi_device) is used.
> + * @dummy_data: indicates transfer is dummy bytes transfer.
>   * @cs_change: affects chipselect after this transfer completes
>   * @cs_change_delay: delay between cs deassert and assert when
>   *      @cs_change is set and @spi_transfer is not the last in @spi_message
> @@ -939,6 +940,7 @@ struct spi_transfer {
>  	struct sg_table tx_sg;
>  	struct sg_table rx_sg;
>  
> +	unsigned	dummy_data:1;
>  	unsigned	cs_change:1;
>  	unsigned	tx_nbits:3;
>  	unsigned	rx_nbits:3;
> -- 
> 2.7.4
> 

-- 
Regards,
Pratyush Yadav
Texas Instruments India

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ