linux-kernel - Re: [PATCH resend] clk: si5351: Wait for bit clear after PLL reset

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Message-ID: <160842180913.1580929.4780279179860483552@swboyd.mtv.corp.google.com>
Date:   Sat, 19 Dec 2020 15:50:09 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Sascha Hauer <s.hauer@...gutronix.de>, linux-clk@...r.kernel.org
Cc:     Michael Turquette <mturquette@...libre.com>,
        linux-kernel@...r.kernel.org,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        Sascha Hauer <s.hauer@...gutronix.de>
Subject: Re: [PATCH resend] clk: si5351: Wait for bit clear after PLL reset

Quoting Sascha Hauer (2020-11-30 01:10:33)
> Documentation states that SI5351_PLL_RESET_B and SI5351_PLL_RESET_A bits
> are self clearing bits, so wait until they are cleared before
> continuing.
> This fixes a case when the clock doesn't come up properly after a PLL
> reset. It worked properly when the frequency was below 900MHz, but with
> 900MHz it only works when we are waiting for the bit to clear.
> 
> Signed-off-by: Sascha Hauer <s.hauer@...gutronix.de>
> ---

Applied to clk-next