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Date: Sat, 19 Dec 2020 11:57:20 +0100 From: Krzysztof Kozlowski <krzk@...nel.org> To: Dmitry Osipenko <digetx@...il.com> Cc: Thierry Reding <thierry.reding@...il.com>, Jonathan Hunter <jonathanh@...dia.com>, Mark Brown <broonie@...nel.org>, Liam Girdwood <lgirdwood@...il.com>, Ulf Hansson <ulf.hansson@...aro.org>, Mauro Carvalho Chehab <mchehab@...nel.org>, Rob Herring <robh+dt@...nel.org>, Peter Geis <pgwipeout@...il.com>, Nicolas Chauvet <kwizart@...il.com>, "Rafael J. Wysocki" <rjw@...ysocki.net>, Kevin Hilman <khilman@...nel.org>, Peter De Schrijver <pdeschrijver@...dia.com>, Viresh Kumar <vireshk@...nel.org>, Stephen Boyd <sboyd@...nel.org>, Michael Turquette <mturquette@...libre.com>, devel@...verdev.osuosl.org, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org, linux-media@...r.kernel.org, linux-tegra@...r.kernel.org, linux-clk@...r.kernel.org Subject: Re: [PATCH v2 07/48] dt-bindings: arm: tegra: Add binding for core power domain On Thu, Dec 17, 2020 at 09:05:57PM +0300, Dmitry Osipenko wrote: > All NVIDIA Tegra SoCs have a core power domain where majority of hardware > blocks reside. Add binding for the core power domain. > > Signed-off-by: Dmitry Osipenko <digetx@...il.com> > --- > .../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 +++++++++++++++++++ > 1 file changed, 48 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml > > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml > new file mode 100644 > index 000000000000..f3d8fd2d8371 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-core-domain.yaml > @@ -0,0 +1,48 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-core-domain.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra Core Power Domain > + > +maintainers: > + - Dmitry Osipenko <digetx@...il.com> > + - Jon Hunter <jonathanh@...dia.com> > + - Thierry Reding <thierry.reding@...il.com> > + > +properties: > + compatible: > + enum: > + - nvidia,tegra20-core-domain > + - nvidia,tegra30-core-domain The file should be in bindings/power. Include also the power-domain.yaml schema. > + > + operating-points-v2: > + description: > + Should contain level, voltages and opp-supported-hw property. > + The supported-hw is a bitfield indicating SoC speedo or process > + ID mask. > + > + "#power-domain-cells": > + const: 0 > + > + power-supply: > + description: > + Phandle to voltage regulator connected to the SoC Core power rail. > + > +required: > + - compatible > + - operating-points-v2 > + - "#power-domain-cells" > + - power-supply > + > +additionalProperties: false > + > +examples: > + - | > + core-domain { power-domain (to follow schema and devicetree spec) Best regards, Krzysztof > + compatible = "nvidia,tegra20-core-domain"; > + operating-points-v2 = <&opp_table>; > + power-supply = <®ulator>; > + #power-domain-cells = <0>; > + }; > -- > 2.29.2 >
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