Message-ID: <6645f038-7101-67e4-0843-35125f74597a@gmail.com>
Date:   Sun, 20 Dec 2020 16:58:59 -0800
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Steen Hegelund <steen.hegelund@...rochip.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>
Cc:     Andrew Lunn <andrew@...n.ch>, Russell King <linux@...linux.org.uk>,
        Lars Povlsen <lars.povlsen@...rochip.com>,
        Bjarni Jonasson <bjarni.jonasson@...rochip.com>,
        Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Madalin Bucur <madalin.bucur@....nxp.com>,
        Nicolas Ferre <nicolas.ferre@...rochip.com>,
        Mark Einon <mark.einon@...il.com>,
        Masahiro Yamada <masahiroy@...nel.org>,
        Arnd Bergmann <arnd@...db.de>, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [RFC PATCH v2 0/8] Adding the Sparx5 Switch Driver



On 12/16/2020 11:51 PM, Steen Hegelund wrote:
> This series provides the Microchip Sparx5 Switch Driver
> 
> The Sparx5 Carrier Ethernet and Industrial switch family delivers 64
> Ethernet ports and up to 200 Gbps of switching bandwidth.
> 
> It provides a rich set of Ethernet switching features such as hierarchical
> QoS, hardware-based OAM  and service activation testing, protection
> switching, IEEE 1588, and Synchronous Ethernet.
> 
> Using provider bridging (Q-in-Q) and MPLS/MPLS-TP technology, it delivers
> MEF CE
> 2.0 Ethernet virtual connections (EVCs) and features advanced TCAM
>   classification in both ingress and egress.
> 
> Per-EVC features include advanced L3-aware classification, a rich set of
> statistics, OAM for end-to-end performance monitoring, and dual-rate
> policing and shaping.
> 
> Time sensitive networking (TSN) is supported through a comprehensive set of
> features including frame preemption, cut-through, frame replication and
> elimination for reliability, enhanced scheduling: credit-based shaping,
> time-aware shaping, cyclic queuing, and forwarding, and per-stream policing
> and filtering.
> 
> Together with IEEE 1588 and IEEE 802.1AS support, this guarantees
> low-latency deterministic networking for Fronthaul, Carrier, and Industrial
> Ethernet.
> 
> The Sparx5 switch family consists of following SKUs:
> 
> - VSC7546 Sparx5-64 up to 64 Gbps of bandwidth with the following primary
>   port configurations:
>   - 6 *10G
>   - 16 * 2.5G + 2 * 10G
>   - 24 * 1G + 4 * 10G
> 
> - VSC7549 Sparx5-90 up to 90 Gbps of bandwidth with the following primary
>   port configurations:
>   - 9 * 10G
>   - 16 * 2.5G + 4 * 10G
>   - 48 * 1G + 4 * 10G
> 
> - VSC7552 Sparx5-128 up to 128 Gbps of bandwidth with the following primary
>   port configurations:
>   - 12 * 10G
>   - 16 * 2.5G + 8 * 10G
>   - 48 * 1G + 8 * 10G
> 
> - VSC7556 Sparx5-160 up to 160 Gbps of bandwidth with the following primary
>   port configurations:
>   - 16 * 10G
>   - 10 * 10G + 2 * 25G
>   - 16 * 2.5G + 10 * 10G
>   - 48 * 1G + 10 * 10G
> 
> - VSC7558 Sparx5-200 up to 200 Gbps of bandwidth with the following primary
>   port configurations:
>   - 20 * 10G
>   - 8 * 25G
> 
> In addition, the device supports one 10/100/1000/2500/5000 Mbps
> SGMII/SerDes node processor interface (NPI) Ethernet port.
> 
> The Sparx5 support is developed on the PCB134 and PCB135 evaluation boards.
> 
> - PCB134 main networking features:
>   - 12x SFP+ front 10G module slots (connected to Sparx5 through SFI).
>   - 8x SFP28 front 25G module slots (connected to Sparx5 through SFI high
>     speed).
>   - Optional, one additional 10/100/1000BASE-T (RJ45) Ethernet port
>     (on-board VSC8211 PHY connected to Sparx5 through SGMII).
> 
> - PCB135 main networking features:
>   - 48x1G (10/100/1000M) RJ45 front ports using 12xVSC8514 QuadPHY’s each
>     connected to VSC7558 through QSGMII.
>   - 4x10G (1G/2.5G/5G/10G) RJ45 front ports using the AQR407 10G QuadPHY
>     each port connects to VSC7558 through SFI.
>   - 4x SFP28 25G module slots on back connected to VSC7558 through SFI high
>     speed.
>   - Optional, one additional 1G (10/100/1000M) RJ45 port using an on-board
>     VSC8211 PHY, which can be connected to VSC7558 NPI port through SGMII
>     using a loopback add-on PCB)
> 
> This series provides support for:
>   - SFPs and DAC cables via PHYLINK with a number of 5G, 10G and 25G
>     devices and media types.
>   - Port module configuration for 10M to 25G speeds with SGMII, QSGMII,
>     1000BASEX, 2500BASEX and 10GBASER as appropriate for these modes.
>   - SerDes configuration via the Sparx5 SerDes driver (see below).
>   - Host mode providing register based injection and extraction.
>   - Switch mode providing MAC/VLAN table learning and Layer2 switching
>     offloaded to the Sparx5 switch.
>   - STP state, VLAN support, host/bridge port mode, Forwarding DB, and
>     configuration and statistics via ethtool.
> 
> More support will be added at a later stage.
> 
> The Sparx5 Switch chip register model can be browsed here:
> Link: https://microchip-ung.github.io/sparx-5_reginfo/reginfo_sparx-5.html

Out of curiosity, what tool was used to generate the register
information page? It looks really neat and well organized.
-- 
Florian

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