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Date: Tue, 22 Dec 2020 12:35:17 +0530
From: Kishon Vijay Abraham I <kishon@...com>
To: Kishon Vijay Abraham I <kishon@...com>,
Vinod Koul <vkoul@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Swapnil Jakhade <sjakhade@...ence.com>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
CC: Nishanth Menon <nm@...com>, Philipp Zabel <p.zabel@...gutronix.de>
Subject: [PATCH v2 11/14] arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES
Add DT nodes for clocks within Sierra SERDES.
Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 128 ++++++++++++++++++++--
1 file changed, 120 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index b32df591c766..00d2d51689f1 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -432,8 +432,36 @@
#size-cells = <0>;
resets = <&serdes_wiz0 0>;
reset-names = "sierra_reset";
- clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>, <&serdes0_pll_cmnlc>, <&serdes0_pll_cmnlc1>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+ serdes0_refrcv: refrcv {
+ clocks = <&wiz0_pll0_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes0_refrcv1: refrcv1 {
+ clocks = <&wiz0_pll1_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes0_pll_cmnlc: pll_cmnlc {
+ clocks = <&wiz0_pll0_refclk>, <&serdes0_refrcv1>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes0_pll_cmnlc>;
+ assigned-clock-parents = <&wiz0_pll0_refclk>;
+ };
+
+ serdes0_pll_cmnlc1: pll_cmnlc1 {
+ clocks = <&wiz0_pll1_refclk>, <&serdes0_refrcv>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes0_pll_cmnlc1>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
+ };
};
};
@@ -489,8 +517,36 @@
#size-cells = <0>;
resets = <&serdes_wiz1 0>;
reset-names = "sierra_reset";
- clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>, <&serdes1_pll_cmnlc>, <&serdes1_pll_cmnlc1>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+ serdes1_refrcv: refrcv {
+ clocks = <&wiz1_pll0_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes1_refrcv1: refrcv1 {
+ clocks = <&wiz1_pll1_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes1_pll_cmnlc: pll_cmnlc {
+ clocks = <&wiz1_pll0_refclk>, <&serdes1_refrcv1>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes1_pll_cmnlc>;
+ assigned-clock-parents = <&wiz1_pll0_refclk>;
+ };
+
+ serdes1_pll_cmnlc1: pll_cmnlc1 {
+ clocks = <&wiz1_pll1_refclk>, <&serdes1_refrcv>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes1_pll_cmnlc1>;
+ assigned-clock-parents = <&wiz1_pll1_refclk>;
+ };
};
};
@@ -546,8 +602,36 @@
#size-cells = <0>;
resets = <&serdes_wiz2 0>;
reset-names = "sierra_reset";
- clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>, <&serdes2_pll_cmnlc>, <&serdes2_pll_cmnlc1>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+ serdes2_refrcv: refrcv {
+ clocks = <&wiz2_pll0_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes2_refrcv1: refrcv1 {
+ clocks = <&wiz2_pll1_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes2_pll_cmnlc: pll_cmnlc {
+ clocks = <&wiz2_pll0_refclk>, <&serdes2_refrcv1>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes2_pll_cmnlc>;
+ assigned-clock-parents = <&wiz2_pll0_refclk>;
+ };
+
+ serdes2_pll_cmnlc1: pll_cmnlc1 {
+ clocks = <&wiz2_pll1_refclk>, <&serdes2_refrcv>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes2_pll_cmnlc1>;
+ assigned-clock-parents = <&wiz2_pll1_refclk>;
+ };
};
};
@@ -603,8 +687,36 @@
#size-cells = <0>;
resets = <&serdes_wiz3 0>;
reset-names = "sierra_reset";
- clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>, <&serdes3_pll_cmnlc>, <&serdes3_pll_cmnlc1>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div", "pll_cmnlc", "pll_cmnlc1";
+
+ serdes3_refrcv: refrcv {
+ clocks = <&wiz3_pll0_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes3_refrcv1: refrcv1 {
+ clocks = <&wiz3_pll1_refclk>;
+ clock-names = "pll_refclk";
+ #clock-cells = <0>;
+ };
+
+ serdes3_pll_cmnlc: pll_cmnlc {
+ clocks = <&wiz3_pll0_refclk>, <&serdes3_refrcv1>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes3_pll_cmnlc>;
+ assigned-clock-parents = <&wiz3_pll0_refclk>;
+ };
+
+ serdes3_pll_cmnlc1: pll_cmnlc1 {
+ clocks = <&wiz3_pll1_refclk>, <&serdes3_refrcv>;
+ clock-names = "pll_refclk", "refrcv";
+ #clock-cells = <0>;
+ assigned-clocks = <&serdes3_pll_cmnlc1>;
+ assigned-clock-parents = <&wiz3_pll1_refclk>;
+ };
};
};
--
2.17.1
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