| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Tue, 22 Dec 2020 08:30:41 +0100
From: Steen Hegelund <steen.hegelund@...rochip.com>
To: Rob Herring <robh@...nel.org>
CC: "David S. Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Device Tree List <devicetree@...r.kernel.org>,
Andrew Lunn <andrew@...n.ch>,
Russell King <linux@...linux.org.uk>,
Lars Povlsen <lars.povlsen@...rochip.com>,
Bjarni Jonasson <bjarni.jonasson@...rochip.com>,
Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Madalin Bucur <madalin.bucur@....nxp.com>,
Nicolas Ferre <nicolas.ferre@...rochip.com>,
Mark Einon <mark.einon@...il.com>,
Masahiro Yamada <masahiroy@...nel.org>,
"Arnd Bergmann" <arnd@...db.de>, <netdev@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [RFC PATCH v2 1/8] dt-bindings: net: sparx5: Add sparx5-switch
bindings
Hi Rob,
On Mon, 2020-12-21 at 14:40 -0700, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
>
> On Thu, Dec 17, 2020 at 08:51:27AM +0100, Steen Hegelund wrote:
> > Document the Sparx5 switch device driver bindings
> >
> > Signed-off-by: Steen Hegelund <steen.hegelund@...rochip.com>
> > Signed-off-by: Lars Povlsen <lars.povlsen@...rochip.com>
> > ---
> > .../bindings/net/microchip,sparx5-switch.yaml | 178
> > ++++++++++++++++++
> > 1 file changed, 178 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/net/microchip,sparx5-
> > switch.yaml
> > b/Documentation/devicetree/bindings/net/microchip,sparx5-
> > switch.yaml
> > new file mode 100644
> > index 000000000000..6e3ef8285e9a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-
> > switch.yaml
> > @@ -0,0 +1,178 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id:
> > http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Microchip Sparx5 Ethernet switch controller
> > +
> > +maintainers:
> > + - Lars Povlsen <lars.povlsen@...rochip.com>
> > + - Steen Hegelund <steen.hegelund@...rochip.com>
> > +
> > +description: |
> > + The SparX-5 Enterprise Ethernet switch family provides a rich
> > set of
> > + Enterprise switching features such as advanced TCAM-based VLAN
> > and
> > + QoS processing enabling delivery of differentiated services, and
> > + security through TCAM-based frame processing using versatile
> > content
> > + aware processor (VCAP).
> > +
> > + IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is
> > supported
> > + with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K
> > IPv4/3K
> > + IPv6 (S,G) multicast groups.
> > +
> > + L3 security features include source guard and reverse path
> > + forwarding (uRPF) tasks. Additional L3 features include VRF-Lite
> > and
> > + IP tunnels (IP over GRE/IP).
> > +
> > + The SparX-5 switch family targets managed Layer 2 and Layer 3
> > + equipment in SMB, SME, and Enterprise where high port count
> > + 1G/2.5G/5G/10G switching with 10G/25G aggregation links is
> > required.
> > +
> > +properties:
> > + $nodename:
> > + pattern: "^switch@[0-9a-f]+$"
> > +
> > + compatible:
> > + const: microchip,sparx5-switch
> > +
> > + reg:
> > + minItems: 2
> > +
> > + reg-names:
> > + minItems: 2
>
> This is the default based on 'items' length.
Does that mean that I should omit minItems here?
>
> > + items:
> > + - const: devices
> > + - const: gcb
> > +
> > + interrupts:
> > + maxItems: 1
> > + description: Interrupt used for reception of packets to the
> > CPU
> > +
> > + ethernet-ports:
> > + type: object
> > + properties:
> > + '#address-cells':
> > + const: 1
> > + '#size-cells':
> > + const: 0
> > +
> > + patternProperties:
> > + "^port@[0-9]+$":
> > + type: object
> > + description: Switch ports
> > +
> > + allOf:
> > + - $ref: ethernet-controller.yaml#
> > +
> > + properties:
> > + reg:
> > + description: Switch port number
> > +
> > + max-speed:
> > + maxItems: 1
>
> Is that an array?
No it is just a single value.
>
> > + description: Bandwidth allocated to this port
> > +
> > + phys:
>
> How many? (maxItems)
I will add "maxItems: 1"
>
> > + description: phandle of a Ethernet Serdes PHY
> > +
> > + phy-handle:
> > + description: phandle of a Ethernet PHY
> > +
> > + phy-mode:
> > + description: Interface between the serdes and the phy
>
> The whole set of modes defined is supported?
This driver does not impose any limits on phy-mode. It is passed on to
the phy, so all modes are supported as I see it.
>
> > +
> > + sfp:
> > + description: phandle of an SFP
> > +
> > + managed:
> > + maxItems: 1
>
> An array?
No just a single item.
Thanks for your comments.
BR
Steen
>
> > + description: SFP management
> > +
> > + required:
> > + - reg
> > + - max-speed
> > + - phys
> > +
> > + oneOf:
> > + - required:
> > + - phy-handle
> > + - phy-mode
> > + - required:
> > + - sfp
> > + - managed
> > +
> > + additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - interrupts
> > + - ethernet-ports
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + switch: switch@...000000 {
> > + compatible = "microchip,sparx5-switch";
> > + reg = <0x10000000 0x800000>,
> > + <0x11010000 0x1b00000>;
> > + reg-names = "devices", "gcb";
> > +
> > + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> > + ethernet-ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port0: port@0 {
> > + reg = <0>;
> > + max-speed = <1000>;
> > + phys = <&serdes 13>;
> > + phy-handle = <&phy0>;
> > + phy-mode = "qsgmii";
> > + };
> > + /* ... */
> > + /* Then the 25G interfaces */
> > + port60: port@60 {
> > + reg = <60>;
> > + max-speed = <25000>;
> > + phys = <&serdes 29>;
> > + sfp = <&sfp_eth60>;
> > + managed = "in-band-status";
> > + };
> > + port61: port@61 {
> > + reg = <61>;
> > + max-speed = <25000>;
> > + phys = <&serdes 30>;
> > + sfp = <&sfp_eth61>;
> > + managed = "in-band-status";
> > + };
> > + port62: port@62 {
> > + reg = <62>;
> > + max-speed = <25000>;
> > + phys = <&serdes 31>;
> > + sfp = <&sfp_eth62>;
> > + managed = "in-band-status";
> > + };
> > + port63: port@63 {
> > + reg = <63>;
> > + max-speed = <25000>;
> > + phys = <&serdes 32>;
> > + sfp = <&sfp_eth63>;
> > + managed = "in-band-status";
> > + };
> > + /* Finally the Management interface */
> > + port64: port@64 {
> > + reg = <64>;
> > + max-speed = <1000>;
> > + phys = <&serdes 0>;
> > + phy-handle = <&phy64>;
> > + phy-mode = "sgmii";
> > + };
> > + };
> > + };
> > +
> > +...
> > --
> > 2.29.2
> >
Powered by blists - more mailing lists