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Message-ID: <CAMuHMdV2hnNoZdLme=BRKz9vfGe22ZUCw6HiJM5ZUvhU2=P0rA@mail.gmail.com>
Date: Tue, 22 Dec 2020 10:13:49 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Wolfram Sang <wsa+renesas@...g-engineering.com>
Cc: Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
Magnus Damm <magnus.damm@...il.com>,
Rob Herring <robh+dt@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/5] arm64: dts: renesas: r8a779a0: Add RWDT node
On Fri, Dec 18, 2020 at 6:37 PM Wolfram Sang
<wsa+renesas@...g-engineering.com> wrote:
> From: Hoang Vo <hoang.vo.eb@...esas.com>
>
> Add a device node for the Watchdog Timer (WDT) controller on the
> R8A779A0 SoC.
>
> Signed-off-by: Hoang Vo <hoang.vo.eb@...esas.com>
> [wsa: rebased to mainline]
> Signed-off-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
i.e. will queue in renesas-devel for v5.12 (with sort order fixed).
> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -85,6 +85,16 @@ rst: reset-controller@...60000 {
> reg = <0 0xe6160000 0 0x4000>;
> };
>
> + rwdt: watchdog@...20000 {
> + compatible = "renesas,r8a779a0-wdt",
> + "renesas,rcar-gen3-wdt";
> + reg = <0 0xe6020000 0 0x0c>;
> + clocks = <&cpg CPG_MOD 907>;
> + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
> + resets = <&cpg 907>;
> + status = "disabled";
No interrupts property? ;-)
As we don't have it described yet for the other R-Car Gen3 SoCs, I
suggest we do that in one batch...
> + };
> +
> sysc: system-controller@...80000 {
> compatible = "renesas,r8a779a0-sysc";
> reg = <0 0xe6180000 0 0x4000>;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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