linux-kernel - Re: [PATCH v2 06/48] dt-bindings: clock: tegra: Document clocks sub-node

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Message-ID: <c4ce87e9-0e8d-a0cb-6098-f98e285ebf75@gmail.com>
Date:   Tue, 22 Dec 2020 22:16:28 +0300
From:   Dmitry Osipenko <digetx@...il.com>
To:     Rob Herring <robh@...nel.org>
Cc:     Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Mark Brown <broonie@...nel.org>,
        Liam Girdwood <lgirdwood@...il.com>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Peter Geis <pgwipeout@...il.com>,
        Nicolas Chauvet <kwizart@...il.com>,
        Krzysztof Kozlowski <krzk@...nel.org>,
        "Rafael J. Wysocki" <rjw@...ysocki.net>,
        Kevin Hilman <khilman@...nel.org>,
        Peter De Schrijver <pdeschrijver@...dia.com>,
        Viresh Kumar <vireshk@...nel.org>,
        Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        devel@...verdev.osuosl.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org,
        linux-media@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 06/48] dt-bindings: clock: tegra: Document clocks
 sub-node

22.12.2020 03:14, Rob Herring пишет:
> On Thu, Dec 17, 2020 at 09:05:56PM +0300, Dmitry Osipenko wrote:
>> Document "clocks" sub-node which describes Tegra SoC clocks that require
>> a higher voltage of the core power domain in order to operate properly on
>> a higher rates.
> 
> Seems like an odd reason to have a bunch of child nodes. It very much 
> seems like a problem you'd need to solve after you design the binding 
> which should be fixed within the kernel.

The reason is that multiple root SoC PLL clocks need to have individual
OPP table because proper voltage should be maintained for these clocks
based on the clock rate.

Some of the clocks do not belong to any specific device and there is a
need to specify the OPP table for them. Each child node represents an
individual clock with the clock's OPP table and power domain.

Some clocks belong to a specific device, but don't require high voltages
and it's very convenient that clk device could manage voltage for these
clocks, instead of populating each device with OPP support (PWM, MMC and
etc).

I'll update the commit message with a better explanation in v3.

> This is also above my threshold for 'convert to schema' first...

Alright, will convert it in v3.