linux-kernel - Re: [PATCH v1, 3/5] mailbox: mediatek: add control_by

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Message-ID: <1608683595.18252.0.camel@mhfsdcap03>
Date:   Wed, 23 Dec 2020 08:33:15 +0800
From:   Yongqiang Niu <yongqiang.niu@...iatek.com>
To:     Nicolas Boichat <drinkcat@...omium.org>
CC:     Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        CK Hu <ck.hu@...iatek.com>,
        Jassi Brar <jassisinghbrar@...il.com>,
        Bibby Hsieh <bibby.hsieh@...iatek.com>,
        "Dennis YC Hsieh" <dennis-yc.hsieh@...iatek.com>,
        linux-arm Mailing List <linux-arm-kernel@...ts.infradead.org>,
        "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@...ts.infradead.org>,
        lkml <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1, 3/5] mailbox: mediatek: add control_by_sw private
 data

On Sat, 2020-12-05 at 15:35 +0800, Nicolas Boichat wrote:
> On Sat, Dec 5, 2020 at 12:18 PM Yongqiang Niu
> <yongqiang.niu@...iatek.com> wrote:
> >
> > add control_by_sw private data
> 
> Can you describe in a bit more details what this means?

gce works well without this patch, and it will be removed in
next version
> 
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@...iatek.com>
> > ---
> >  drivers/mailbox/mtk-cmdq-mailbox.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> > index 5665b6e..1c01fe0 100644
> > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > @@ -36,6 +36,8 @@
> >  #define CMDQ_THR_WAIT_TOKEN            0x30
> >  #define CMDQ_THR_PRIORITY              0x40
> >
> > +#define GCE_GCTL_VALUE                 0x48
> > +
> >  #define CMDQ_THR_ACTIVE_SLOT_CYCLES    0x3200
> >  #define CMDQ_THR_ENABLED               0x1
> >  #define CMDQ_THR_DISABLED              0x0
> > @@ -76,11 +78,13 @@ struct cmdq {
> >         struct clk              *clock;
> >         bool                    suspended;
> >         u8                      shift_pa;
> > +       bool                    control_by_sw;
> >  };
> >
> >  struct gce_plat {
> >         u32 thread_nr;
> >         u8 shift;
> > +       bool control_by_sw;
> >  };
> >
> >  u8 cmdq_get_shift_pa(struct mbox_chan *chan)
> > @@ -121,6 +125,8 @@ static void cmdq_init(struct cmdq *cmdq)
> >         int i;
> >
> >         WARN_ON(clk_enable(cmdq->clock) < 0);
> > +       if (cmdq->control_by_sw)
> > +               writel(0x7, cmdq->base + GCE_GCTL_VALUE);
> 
> What is 0x7? Define a macro for these bits?
> 
> >         writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
> >         for (i = 0; i <= CMDQ_MAX_EVENT; i++)
> >                 writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
> > @@ -536,6 +542,7 @@ static int cmdq_probe(struct platform_device *pdev)
> >
> >         cmdq->thread_nr = plat_data->thread_nr;
> >         cmdq->shift_pa = plat_data->shift;
> > +       cmdq->control_by_sw = plat_data->control_by_sw;
> >         cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
> >         err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
> >                                "mtk_cmdq", cmdq);
> > --
> > 1.8.1.1.dirty
> >