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Date: Thu, 24 Dec 2020 08:48:08 +0800 From: Yongqiang Niu <yongqiang.niu@...iatek.com> To: CK Hu <ck.hu@...iatek.com>, Philipp Zabel <p.zabel@...gutronix.de>, Rob Herring <robh+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com> CC: David Airlie <airlied@...ux.ie>, Daniel Vetter <daniel@...ll.ch>, Mark Rutland <mark.rutland@....com>, <dri-devel@...ts.freedesktop.org>, <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>, <Project_Global_Chrome_Upstream_Group@...iatek.com>, Yongqiang Niu <yongqiang.niu@...iatek.com> Subject: [PATCH v2, 2/3] arm64: dts: mt8192: add gce node add gce node Signed-off-by: Yongqiang Niu <yongqiang.niu@...iatek.com> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 69d45c7..e9684a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/clock/mt8192-clk.h> +#include <dt-bindings/gce/mt8192-gce.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/pinctrl/mt8192-pinfunc.h> @@ -272,6 +273,15 @@ clock-names = "clk13m"; }; + gce: mailbox@...28000 { + compatible = "mediatek,mt8192-gce"; + reg = <0 0x10228000 0 0x4000>; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <3>; + clocks = <&infracfg CLK_INFRA_GCE>; + clock-names = "gce"; + }; + scp_adsp: syscon@...20000 { compatible = "mediatek,mt8192-scp_adsp", "syscon"; reg = <0 0x10720000 0 0x1000>; -- 1.8.1.1.dirty
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