lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Date:   Sat, 26 Dec 2020 13:15:53 +0100
From:   Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To:     linux-amlogic@...ts.infradead.org, jbrunet@...libre.com
Cc:     mturquette@...libre.com, sboyd@...nel.org,
        linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Subject: [PATCH 0/3] clk: meson: three small clk-pll fixes

Hi Jerome,

while working on some changes for the 32-bit SoCs I hit a corner-case
in the HDMI PLL: there's some rate doubling going. The PLL only locks
in a specific rate range but the M/N table is not aware of that. This
means for now (I am planning to fix that) that we can end up in a 
ituation where the PLL doesn't lock and meson_clk_pll_set_rate() is
supposed to still behave in this case. So here's three small patches
for that.

For me it's fine to queue these patches for -next. I am not aware of
any breakage upstream, only some of my pending patches prefer to have
these fixes.

Slightly unrelated: if you know anything about that clock doubling then
please let me know!


Best regards,
Martin


Martin Blumenstingl (3):
  clk: meson: clk-pll: fix initializing the old rate (fallback) for a
    PLL
  clk: meson: clk-pll: make "ret" a signed integer
  clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()

 drivers/clk/meson/clk-pll.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

-- 
2.29.2

Powered by blists - more mailing lists