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Date:   Tue, 29 Dec 2020 14:30:03 +0800
From:   kernel test robot <lkp@...el.com>
To:     Luc Van Oostenryck <luc.vanoostenryck@...il.com>
Cc:     kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org,
        Miguel Ojeda <miguel.ojeda.sandonis@...il.com>
Subject: drivers/net/wan/fsl_ucc_hdlc.c:305:17: sparse: sparse: incorrect
 type in argument 1 (different address spaces)

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   dea8dcf2a9fa8cc540136a6cd885c3beece16ec3
commit: e5fc436f06eef54ef512ea55a9db8eb9f2e76959 sparse: use static inline for __chk_{user,io}_ptr()
date:   4 months ago
config: arm-randconfig-s031-20201221 (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.3-184-g1b896707-dirty
        # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e5fc436f06eef54ef512ea55a9db8eb9f2e76959
        git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
        git fetch --no-tags linus master
        git checkout e5fc436f06eef54ef512ea55a9db8eb9f2e76959
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=arm 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>


"sparse warnings: (new ones prefixed by >>)"
>> drivers/net/wan/fsl_ucc_hdlc.c:305:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:305:17: sparse:     expected void const volatile [noderef] __iomem *ptr
   drivers/net/wan/fsl_ucc_hdlc.c:305:17: sparse:     got restricted __be16 *
   drivers/net/wan/fsl_ucc_hdlc.c:306:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@     expected void volatile [noderef] __iomem *addr @@     got restricted __be32 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:306:17: sparse:     expected void volatile [noderef] __iomem *addr
   drivers/net/wan/fsl_ucc_hdlc.c:306:17: sparse:     got restricted __be32 *
   drivers/net/wan/fsl_ucc_hdlc.c:316:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:316:17: sparse:     expected void const volatile [noderef] __iomem *ptr
   drivers/net/wan/fsl_ucc_hdlc.c:316:17: sparse:     got restricted __be16 *
   drivers/net/wan/fsl_ucc_hdlc.c:317:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@     expected void volatile [noderef] __iomem *addr @@     got restricted __be32 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:317:17: sparse:     expected void volatile [noderef] __iomem *addr
   drivers/net/wan/fsl_ucc_hdlc.c:317:17: sparse:     got restricted __be32 *
   drivers/net/wan/fsl_ucc_hdlc.c:368:29: sparse: sparse: incorrect type in assignment (different base types) @@     expected unsigned short [usertype] @@     got restricted __be16 [usertype] @@
   drivers/net/wan/fsl_ucc_hdlc.c:368:29: sparse:     expected unsigned short [usertype]
   drivers/net/wan/fsl_ucc_hdlc.c:368:29: sparse:     got restricted __be16 [usertype]
   drivers/net/wan/fsl_ucc_hdlc.c:375:36: sparse: sparse: restricted __be16 degrades to integer
   drivers/net/wan/fsl_ucc_hdlc.c:398:12: sparse: sparse: incorrect type in assignment (different address spaces) @@     expected struct qe_bd [noderef] __iomem *bd @@     got struct qe_bd *curtx_bd @@
   drivers/net/wan/fsl_ucc_hdlc.c:398:12: sparse:     expected struct qe_bd [noderef] __iomem *bd
   drivers/net/wan/fsl_ucc_hdlc.c:398:12: sparse:     got struct qe_bd *curtx_bd
   drivers/net/wan/fsl_ucc_hdlc.c:408:35: sparse: sparse: dereference of noderef expression
   drivers/net/wan/fsl_ucc_hdlc.c:421:20: sparse: sparse: incorrect type in assignment (different address spaces) @@     expected struct qe_bd [noderef] __iomem *[assigned] bd @@     got struct qe_bd *tx_bd_base @@
   drivers/net/wan/fsl_ucc_hdlc.c:421:20: sparse:     expected struct qe_bd [noderef] __iomem *[assigned] bd
   drivers/net/wan/fsl_ucc_hdlc.c:421:20: sparse:     got struct qe_bd *tx_bd_base
   drivers/net/wan/fsl_ucc_hdlc.c:423:16: sparse: sparse: incompatible types in comparison expression (different address spaces):
   drivers/net/wan/fsl_ucc_hdlc.c:423:16: sparse:    struct qe_bd [noderef] __iomem *
   drivers/net/wan/fsl_ucc_hdlc.c:423:16: sparse:    struct qe_bd *
   drivers/net/wan/fsl_ucc_hdlc.c:458:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:458:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:458:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:458:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:502:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:502:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:502:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:502:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:524:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:524:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:524:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:524:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:548:26: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:548:26: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:548:26: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:548:26: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:592:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:607:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:607:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:607:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:607:29: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void const volatile [noderef] __iomem *ptr @@     got restricted __be16 * @@
   drivers/net/wan/fsl_ucc_hdlc.c:408:35: sparse: sparse: dereference of noderef expression
   drivers/net/wan/fsl_ucc_hdlc.c:408:35: sparse: sparse: dereference of noderef expression
   drivers/net/wan/fsl_ucc_hdlc.c:723:29: sparse: sparse: dereference of noderef expression
   drivers/net/wan/fsl_ucc_hdlc.c:814:21: sparse: sparse: dereference of noderef expression

vim +305 drivers/net/wan/fsl_ucc_hdlc.c

c19b6d246a35627 Zhao Qiang       2016-06-06   77  
c19b6d246a35627 Zhao Qiang       2016-06-06   78  static int uhdlc_init(struct ucc_hdlc_private *priv)
c19b6d246a35627 Zhao Qiang       2016-06-06   79  {
c19b6d246a35627 Zhao Qiang       2016-06-06   80  	struct ucc_tdm_info *ut_info;
c19b6d246a35627 Zhao Qiang       2016-06-06   81  	struct ucc_fast_info *uf_info;
c19b6d246a35627 Zhao Qiang       2016-06-06   82  	u32 cecr_subblock;
c19b6d246a35627 Zhao Qiang       2016-06-06   83  	u16 bd_status;
c19b6d246a35627 Zhao Qiang       2016-06-06   84  	int ret, i;
c19b6d246a35627 Zhao Qiang       2016-06-06   85  	void *bd_buffer;
c19b6d246a35627 Zhao Qiang       2016-06-06   86  	dma_addr_t bd_dma_addr;
be2e9415f8b366a Rasmus Villemoes 2019-11-28   87  	s32 riptr;
be2e9415f8b366a Rasmus Villemoes 2019-11-28   88  	s32 tiptr;
c19b6d246a35627 Zhao Qiang       2016-06-06   89  	u32 gumr;
c19b6d246a35627 Zhao Qiang       2016-06-06   90  
c19b6d246a35627 Zhao Qiang       2016-06-06   91  	ut_info = priv->ut_info;
c19b6d246a35627 Zhao Qiang       2016-06-06   92  	uf_info = &ut_info->uf_info;
c19b6d246a35627 Zhao Qiang       2016-06-06   93  
c19b6d246a35627 Zhao Qiang       2016-06-06   94  	if (priv->tsa) {
c19b6d246a35627 Zhao Qiang       2016-06-06   95  		uf_info->tsa = 1;
c19b6d246a35627 Zhao Qiang       2016-06-06   96  		uf_info->ctsp = 1;
040b7c94e4ec585 David Gounaris   2018-09-03   97  		uf_info->cds = 1;
040b7c94e4ec585 David Gounaris   2018-09-03   98  		uf_info->ctss = 1;
040b7c94e4ec585 David Gounaris   2018-09-03   99  	} else {
040b7c94e4ec585 David Gounaris   2018-09-03  100  		uf_info->cds = 0;
040b7c94e4ec585 David Gounaris   2018-09-03  101  		uf_info->ctsp = 0;
040b7c94e4ec585 David Gounaris   2018-09-03  102  		uf_info->ctss = 0;
c19b6d246a35627 Zhao Qiang       2016-06-06  103  	}
067bb938dad61e5 Holger Brunck    2017-05-17  104  
067bb938dad61e5 Holger Brunck    2017-05-17  105  	/* This sets HPM register in CMXUCR register which configures a
067bb938dad61e5 Holger Brunck    2017-05-17  106  	 * open drain connected HDLC bus
067bb938dad61e5 Holger Brunck    2017-05-17  107  	 */
067bb938dad61e5 Holger Brunck    2017-05-17  108  	if (priv->hdlc_bus)
067bb938dad61e5 Holger Brunck    2017-05-17  109  		uf_info->brkpt_support = 1;
067bb938dad61e5 Holger Brunck    2017-05-17  110  
c19b6d246a35627 Zhao Qiang       2016-06-06  111  	uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
c19b6d246a35627 Zhao Qiang       2016-06-06  112  				UCC_HDLC_UCCE_TXB) << 16);
c19b6d246a35627 Zhao Qiang       2016-06-06  113  
c19b6d246a35627 Zhao Qiang       2016-06-06  114  	ret = ucc_fast_init(uf_info, &priv->uccf);
c19b6d246a35627 Zhao Qiang       2016-06-06  115  	if (ret) {
c19b6d246a35627 Zhao Qiang       2016-06-06  116  		dev_err(priv->dev, "Failed to init uccf.");
c19b6d246a35627 Zhao Qiang       2016-06-06  117  		return ret;
c19b6d246a35627 Zhao Qiang       2016-06-06  118  	}
c19b6d246a35627 Zhao Qiang       2016-06-06  119  
c19b6d246a35627 Zhao Qiang       2016-06-06  120  	priv->uf_regs = priv->uccf->uf_regs;
c19b6d246a35627 Zhao Qiang       2016-06-06  121  	ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
c19b6d246a35627 Zhao Qiang       2016-06-06  122  
c19b6d246a35627 Zhao Qiang       2016-06-06  123  	/* Loopback mode */
c19b6d246a35627 Zhao Qiang       2016-06-06  124  	if (priv->loopback) {
c19b6d246a35627 Zhao Qiang       2016-06-06  125  		dev_info(priv->dev, "Loopback Mode\n");
54e9e0874938ba5 Holger Brunck    2017-05-17  126  		/* use the same clock when work in loopback */
54e9e0874938ba5 Holger Brunck    2017-05-17  127  		qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
54e9e0874938ba5 Holger Brunck    2017-05-17  128  
c19b6d246a35627 Zhao Qiang       2016-06-06  129  		gumr = ioread32be(&priv->uf_regs->gumr);
c19b6d246a35627 Zhao Qiang       2016-06-06  130  		gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
c19b6d246a35627 Zhao Qiang       2016-06-06  131  			 UCC_FAST_GUMR_TCI);
c19b6d246a35627 Zhao Qiang       2016-06-06  132  		gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
c19b6d246a35627 Zhao Qiang       2016-06-06  133  		iowrite32be(gumr, &priv->uf_regs->gumr);
c19b6d246a35627 Zhao Qiang       2016-06-06  134  	}
c19b6d246a35627 Zhao Qiang       2016-06-06  135  
c19b6d246a35627 Zhao Qiang       2016-06-06  136  	/* Initialize SI */
c19b6d246a35627 Zhao Qiang       2016-06-06  137  	if (priv->tsa)
c19b6d246a35627 Zhao Qiang       2016-06-06  138  		ucc_tdm_init(priv->utdm, priv->ut_info);
c19b6d246a35627 Zhao Qiang       2016-06-06  139  
c19b6d246a35627 Zhao Qiang       2016-06-06  140  	/* Write to QE CECR, UCCx channel to Stop Transmission */
c19b6d246a35627 Zhao Qiang       2016-06-06  141  	cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
c19b6d246a35627 Zhao Qiang       2016-06-06  142  	ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
c19b6d246a35627 Zhao Qiang       2016-06-06  143  			   QE_CR_PROTOCOL_UNSPECIFIED, 0);
c19b6d246a35627 Zhao Qiang       2016-06-06  144  
c19b6d246a35627 Zhao Qiang       2016-06-06  145  	/* Set UPSMR normal mode (need fixed)*/
c19b6d246a35627 Zhao Qiang       2016-06-06  146  	iowrite32be(0, &priv->uf_regs->upsmr);
c19b6d246a35627 Zhao Qiang       2016-06-06  147  
067bb938dad61e5 Holger Brunck    2017-05-17  148  	/* hdlc_bus mode */
067bb938dad61e5 Holger Brunck    2017-05-17  149  	if (priv->hdlc_bus) {
067bb938dad61e5 Holger Brunck    2017-05-17  150  		u32 upsmr;
067bb938dad61e5 Holger Brunck    2017-05-17  151  
067bb938dad61e5 Holger Brunck    2017-05-17  152  		dev_info(priv->dev, "HDLC bus Mode\n");
067bb938dad61e5 Holger Brunck    2017-05-17  153  		upsmr = ioread32be(&priv->uf_regs->upsmr);
067bb938dad61e5 Holger Brunck    2017-05-17  154  
067bb938dad61e5 Holger Brunck    2017-05-17  155  		/* bus mode and retransmit enable, with collision window
067bb938dad61e5 Holger Brunck    2017-05-17  156  		 * set to 8 bytes
067bb938dad61e5 Holger Brunck    2017-05-17  157  		 */
067bb938dad61e5 Holger Brunck    2017-05-17  158  		upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
067bb938dad61e5 Holger Brunck    2017-05-17  159  				UCC_HDLC_UPSMR_CW8;
067bb938dad61e5 Holger Brunck    2017-05-17  160  		iowrite32be(upsmr, &priv->uf_regs->upsmr);
067bb938dad61e5 Holger Brunck    2017-05-17  161  
067bb938dad61e5 Holger Brunck    2017-05-17  162  		/* explicitly disable CDS & CTSP */
067bb938dad61e5 Holger Brunck    2017-05-17  163  		gumr = ioread32be(&priv->uf_regs->gumr);
067bb938dad61e5 Holger Brunck    2017-05-17  164  		gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
067bb938dad61e5 Holger Brunck    2017-05-17  165  		/* set automatic sync to explicitly ignore CD signal */
067bb938dad61e5 Holger Brunck    2017-05-17  166  		gumr |= UCC_FAST_GUMR_SYNL_AUTO;
067bb938dad61e5 Holger Brunck    2017-05-17  167  		iowrite32be(gumr, &priv->uf_regs->gumr);
067bb938dad61e5 Holger Brunck    2017-05-17  168  	}
067bb938dad61e5 Holger Brunck    2017-05-17  169  
c19b6d246a35627 Zhao Qiang       2016-06-06  170  	priv->rx_ring_size = RX_BD_RING_LEN;
c19b6d246a35627 Zhao Qiang       2016-06-06  171  	priv->tx_ring_size = TX_BD_RING_LEN;
c19b6d246a35627 Zhao Qiang       2016-06-06  172  	/* Alloc Rx BD */
c19b6d246a35627 Zhao Qiang       2016-06-06  173  	priv->rx_bd_base = dma_alloc_coherent(priv->dev,
5b8aad93c52bdda Holger Brunck    2017-05-17  174  			RX_BD_RING_LEN * sizeof(struct qe_bd),
c19b6d246a35627 Zhao Qiang       2016-06-06  175  			&priv->dma_rx_bd, GFP_KERNEL);
c19b6d246a35627 Zhao Qiang       2016-06-06  176  
c19b6d246a35627 Zhao Qiang       2016-06-06  177  	if (!priv->rx_bd_base) {
c19b6d246a35627 Zhao Qiang       2016-06-06  178  		dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
c19b6d246a35627 Zhao Qiang       2016-06-06  179  		ret = -ENOMEM;
1efb597d8bf56cb Zhao Qiang       2016-07-15  180  		goto free_uccf;
c19b6d246a35627 Zhao Qiang       2016-06-06  181  	}
c19b6d246a35627 Zhao Qiang       2016-06-06  182  
c19b6d246a35627 Zhao Qiang       2016-06-06  183  	/* Alloc Tx BD */
c19b6d246a35627 Zhao Qiang       2016-06-06  184  	priv->tx_bd_base = dma_alloc_coherent(priv->dev,
5b8aad93c52bdda Holger Brunck    2017-05-17  185  			TX_BD_RING_LEN * sizeof(struct qe_bd),
c19b6d246a35627 Zhao Qiang       2016-06-06  186  			&priv->dma_tx_bd, GFP_KERNEL);
c19b6d246a35627 Zhao Qiang       2016-06-06  187  
c19b6d246a35627 Zhao Qiang       2016-06-06  188  	if (!priv->tx_bd_base) {
c19b6d246a35627 Zhao Qiang       2016-06-06  189  		dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n");
c19b6d246a35627 Zhao Qiang       2016-06-06  190  		ret = -ENOMEM;
1efb597d8bf56cb Zhao Qiang       2016-07-15  191  		goto free_rx_bd;
c19b6d246a35627 Zhao Qiang       2016-06-06  192  	}
c19b6d246a35627 Zhao Qiang       2016-06-06  193  
c19b6d246a35627 Zhao Qiang       2016-06-06  194  	/* Alloc parameter ram for ucc hdlc */
85deed56032b6c9 Holger Brunck    2017-05-22  195  	priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
c19b6d246a35627 Zhao Qiang       2016-06-06  196  				ALIGNMENT_OF_UCC_HDLC_PRAM);
c19b6d246a35627 Zhao Qiang       2016-06-06  197  
be2e9415f8b366a Rasmus Villemoes 2019-11-28  198  	if (priv->ucc_pram_offset < 0) {
24a24d07d688a46 Colin Ian King   2016-08-28  199  		dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
c19b6d246a35627 Zhao Qiang       2016-06-06  200  		ret = -ENOMEM;
1efb597d8bf56cb Zhao Qiang       2016-07-15  201  		goto free_tx_bd;
c19b6d246a35627 Zhao Qiang       2016-06-06  202  	}
c19b6d246a35627 Zhao Qiang       2016-06-06  203  
6396bb221514d28 Kees Cook        2018-06-12  204  	priv->rx_skbuff = kcalloc(priv->rx_ring_size,
6396bb221514d28 Kees Cook        2018-06-12  205  				  sizeof(*priv->rx_skbuff),
c19b6d246a35627 Zhao Qiang       2016-06-06  206  				  GFP_KERNEL);
c19b6d246a35627 Zhao Qiang       2016-06-06  207  	if (!priv->rx_skbuff)
1efb597d8bf56cb Zhao Qiang       2016-07-15  208  		goto free_ucc_pram;
c19b6d246a35627 Zhao Qiang       2016-06-06  209  
6396bb221514d28 Kees Cook        2018-06-12  210  	priv->tx_skbuff = kcalloc(priv->tx_ring_size,
6396bb221514d28 Kees Cook        2018-06-12  211  				  sizeof(*priv->tx_skbuff),
c19b6d246a35627 Zhao Qiang       2016-06-06  212  				  GFP_KERNEL);
c19b6d246a35627 Zhao Qiang       2016-06-06  213  	if (!priv->tx_skbuff)
1efb597d8bf56cb Zhao Qiang       2016-07-15  214  		goto free_rx_skbuff;
c19b6d246a35627 Zhao Qiang       2016-06-06  215  
c19b6d246a35627 Zhao Qiang       2016-06-06  216  	priv->skb_curtx = 0;
c19b6d246a35627 Zhao Qiang       2016-06-06  217  	priv->skb_dirtytx = 0;
c19b6d246a35627 Zhao Qiang       2016-06-06  218  	priv->curtx_bd = priv->tx_bd_base;
c19b6d246a35627 Zhao Qiang       2016-06-06  219  	priv->dirty_tx = priv->tx_bd_base;
c19b6d246a35627 Zhao Qiang       2016-06-06  220  	priv->currx_bd = priv->rx_bd_base;
c19b6d246a35627 Zhao Qiang       2016-06-06  221  	priv->currx_bdnum = 0;
c19b6d246a35627 Zhao Qiang       2016-06-06  222  
c19b6d246a35627 Zhao Qiang       2016-06-06  223  	/* init parameter base */
c19b6d246a35627 Zhao Qiang       2016-06-06  224  	cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
c19b6d246a35627 Zhao Qiang       2016-06-06  225  	ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
c19b6d246a35627 Zhao Qiang       2016-06-06  226  			   QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
c19b6d246a35627 Zhao Qiang       2016-06-06  227  
c19b6d246a35627 Zhao Qiang       2016-06-06  228  	priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
c19b6d246a35627 Zhao Qiang       2016-06-06  229  					qe_muram_addr(priv->ucc_pram_offset);
c19b6d246a35627 Zhao Qiang       2016-06-06  230  
c19b6d246a35627 Zhao Qiang       2016-06-06  231  	/* Zero out parameter ram */
c19b6d246a35627 Zhao Qiang       2016-06-06  232  	memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param));
c19b6d246a35627 Zhao Qiang       2016-06-06  233  
c19b6d246a35627 Zhao Qiang       2016-06-06  234  	/* Alloc riptr, tiptr */
c19b6d246a35627 Zhao Qiang       2016-06-06  235  	riptr = qe_muram_alloc(32, 32);
be2e9415f8b366a Rasmus Villemoes 2019-11-28  236  	if (riptr < 0) {
c19b6d246a35627 Zhao Qiang       2016-06-06  237  		dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
c19b6d246a35627 Zhao Qiang       2016-06-06  238  		ret = -ENOMEM;
1efb597d8bf56cb Zhao Qiang       2016-07-15  239  		goto free_tx_skbuff;
c19b6d246a35627 Zhao Qiang       2016-06-06  240  	}
c19b6d246a35627 Zhao Qiang       2016-06-06  241  
c19b6d246a35627 Zhao Qiang       2016-06-06  242  	tiptr = qe_muram_alloc(32, 32);
be2e9415f8b366a Rasmus Villemoes 2019-11-28  243  	if (tiptr < 0) {
c19b6d246a35627 Zhao Qiang       2016-06-06  244  		dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
c19b6d246a35627 Zhao Qiang       2016-06-06  245  		ret = -ENOMEM;
1efb597d8bf56cb Zhao Qiang       2016-07-15  246  		goto free_riptr;
c19b6d246a35627 Zhao Qiang       2016-06-06  247  	}
148587a59f6b858 Rasmus Villemoes 2019-11-28  248  	if (riptr != (u16)riptr || tiptr != (u16)tiptr) {
148587a59f6b858 Rasmus Villemoes 2019-11-28  249  		dev_err(priv->dev, "MURAM allocation out of addressable range\n");
148587a59f6b858 Rasmus Villemoes 2019-11-28  250  		ret = -ENOMEM;
148587a59f6b858 Rasmus Villemoes 2019-11-28  251  		goto free_tiptr;
148587a59f6b858 Rasmus Villemoes 2019-11-28  252  	}
c19b6d246a35627 Zhao Qiang       2016-06-06  253  
c19b6d246a35627 Zhao Qiang       2016-06-06  254  	/* Set RIPTR, TIPTR */
c19b6d246a35627 Zhao Qiang       2016-06-06  255  	iowrite16be(riptr, &priv->ucc_pram->riptr);
c19b6d246a35627 Zhao Qiang       2016-06-06  256  	iowrite16be(tiptr, &priv->ucc_pram->tiptr);
c19b6d246a35627 Zhao Qiang       2016-06-06  257  
c19b6d246a35627 Zhao Qiang       2016-06-06  258  	/* Set MRBLR */
c19b6d246a35627 Zhao Qiang       2016-06-06  259  	iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
c19b6d246a35627 Zhao Qiang       2016-06-06  260  
c19b6d246a35627 Zhao Qiang       2016-06-06  261  	/* Set RBASE, TBASE */
c19b6d246a35627 Zhao Qiang       2016-06-06  262  	iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);
c19b6d246a35627 Zhao Qiang       2016-06-06  263  	iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);
c19b6d246a35627 Zhao Qiang       2016-06-06  264  
c19b6d246a35627 Zhao Qiang       2016-06-06  265  	/* Set RSTATE, TSTATE */
c19b6d246a35627 Zhao Qiang       2016-06-06  266  	iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);
c19b6d246a35627 Zhao Qiang       2016-06-06  267  	iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);
c19b6d246a35627 Zhao Qiang       2016-06-06  268  
c19b6d246a35627 Zhao Qiang       2016-06-06  269  	/* Set C_MASK, C_PRES for 16bit CRC */
c19b6d246a35627 Zhao Qiang       2016-06-06  270  	iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);
c19b6d246a35627 Zhao Qiang       2016-06-06  271  	iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);
c19b6d246a35627 Zhao Qiang       2016-06-06  272  
c19b6d246a35627 Zhao Qiang       2016-06-06  273  	iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
c19b6d246a35627 Zhao Qiang       2016-06-06  274  	iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
c19b6d246a35627 Zhao Qiang       2016-06-06  275  	iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
045f77baf6b429a David Gounaris   2018-09-03  276  	iowrite16be(priv->hmask, &priv->ucc_pram->hmask);
c19b6d246a35627 Zhao Qiang       2016-06-06  277  	iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
c19b6d246a35627 Zhao Qiang       2016-06-06  278  	iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
c19b6d246a35627 Zhao Qiang       2016-06-06  279  	iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
c19b6d246a35627 Zhao Qiang       2016-06-06  280  	iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
c19b6d246a35627 Zhao Qiang       2016-06-06  281  
c19b6d246a35627 Zhao Qiang       2016-06-06  282  	/* Get BD buffer */
750afb08ca71310 Luis Chamberlain 2019-01-04  283  	bd_buffer = dma_alloc_coherent(priv->dev,
750afb08ca71310 Luis Chamberlain 2019-01-04  284  				       (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH,
c19b6d246a35627 Zhao Qiang       2016-06-06  285  				       &bd_dma_addr, GFP_KERNEL);
c19b6d246a35627 Zhao Qiang       2016-06-06  286  
c19b6d246a35627 Zhao Qiang       2016-06-06  287  	if (!bd_buffer) {
c19b6d246a35627 Zhao Qiang       2016-06-06  288  		dev_err(priv->dev, "Could not allocate buffer descriptors\n");
c19b6d246a35627 Zhao Qiang       2016-06-06  289  		ret = -ENOMEM;
1efb597d8bf56cb Zhao Qiang       2016-07-15  290  		goto free_tiptr;
c19b6d246a35627 Zhao Qiang       2016-06-06  291  	}
c19b6d246a35627 Zhao Qiang       2016-06-06  292  
c19b6d246a35627 Zhao Qiang       2016-06-06  293  	priv->rx_buffer = bd_buffer;
c19b6d246a35627 Zhao Qiang       2016-06-06  294  	priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
c19b6d246a35627 Zhao Qiang       2016-06-06  295  
c19b6d246a35627 Zhao Qiang       2016-06-06  296  	priv->dma_rx_addr = bd_dma_addr;
c19b6d246a35627 Zhao Qiang       2016-06-06  297  	priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
c19b6d246a35627 Zhao Qiang       2016-06-06  298  
c19b6d246a35627 Zhao Qiang       2016-06-06  299  	for (i = 0; i < RX_BD_RING_LEN; i++) {
c19b6d246a35627 Zhao Qiang       2016-06-06  300  		if (i < (RX_BD_RING_LEN - 1))
c19b6d246a35627 Zhao Qiang       2016-06-06  301  			bd_status = R_E_S | R_I_S;
c19b6d246a35627 Zhao Qiang       2016-06-06  302  		else
c19b6d246a35627 Zhao Qiang       2016-06-06  303  			bd_status = R_E_S | R_I_S | R_W_S;
c19b6d246a35627 Zhao Qiang       2016-06-06  304  
c19b6d246a35627 Zhao Qiang       2016-06-06 @305  		iowrite16be(bd_status, &priv->rx_bd_base[i].status);
c19b6d246a35627 Zhao Qiang       2016-06-06  306  		iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
c19b6d246a35627 Zhao Qiang       2016-06-06  307  			    &priv->rx_bd_base[i].buf);
c19b6d246a35627 Zhao Qiang       2016-06-06  308  	}
c19b6d246a35627 Zhao Qiang       2016-06-06  309  
c19b6d246a35627 Zhao Qiang       2016-06-06  310  	for (i = 0; i < TX_BD_RING_LEN; i++) {
c19b6d246a35627 Zhao Qiang       2016-06-06  311  		if (i < (TX_BD_RING_LEN - 1))
c19b6d246a35627 Zhao Qiang       2016-06-06  312  			bd_status =  T_I_S | T_TC_S;
c19b6d246a35627 Zhao Qiang       2016-06-06  313  		else
c19b6d246a35627 Zhao Qiang       2016-06-06  314  			bd_status =  T_I_S | T_TC_S | T_W_S;
c19b6d246a35627 Zhao Qiang       2016-06-06  315  
c19b6d246a35627 Zhao Qiang       2016-06-06  316  		iowrite16be(bd_status, &priv->tx_bd_base[i].status);
c19b6d246a35627 Zhao Qiang       2016-06-06  317  		iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
c19b6d246a35627 Zhao Qiang       2016-06-06  318  			    &priv->tx_bd_base[i].buf);
c19b6d246a35627 Zhao Qiang       2016-06-06  319  	}
c19b6d246a35627 Zhao Qiang       2016-06-06  320  
c19b6d246a35627 Zhao Qiang       2016-06-06  321  	return 0;
c19b6d246a35627 Zhao Qiang       2016-06-06  322  
1efb597d8bf56cb Zhao Qiang       2016-07-15  323  free_tiptr:
c19b6d246a35627 Zhao Qiang       2016-06-06  324  	qe_muram_free(tiptr);
1efb597d8bf56cb Zhao Qiang       2016-07-15  325  free_riptr:
c19b6d246a35627 Zhao Qiang       2016-06-06  326  	qe_muram_free(riptr);
1efb597d8bf56cb Zhao Qiang       2016-07-15  327  free_tx_skbuff:
c19b6d246a35627 Zhao Qiang       2016-06-06  328  	kfree(priv->tx_skbuff);
1efb597d8bf56cb Zhao Qiang       2016-07-15  329  free_rx_skbuff:
c19b6d246a35627 Zhao Qiang       2016-06-06  330  	kfree(priv->rx_skbuff);
1efb597d8bf56cb Zhao Qiang       2016-07-15  331  free_ucc_pram:
c19b6d246a35627 Zhao Qiang       2016-06-06  332  	qe_muram_free(priv->ucc_pram_offset);
1efb597d8bf56cb Zhao Qiang       2016-07-15  333  free_tx_bd:
c19b6d246a35627 Zhao Qiang       2016-06-06  334  	dma_free_coherent(priv->dev,
5b8aad93c52bdda Holger Brunck    2017-05-17  335  			  TX_BD_RING_LEN * sizeof(struct qe_bd),
c19b6d246a35627 Zhao Qiang       2016-06-06  336  			  priv->tx_bd_base, priv->dma_tx_bd);
1efb597d8bf56cb Zhao Qiang       2016-07-15  337  free_rx_bd:
c19b6d246a35627 Zhao Qiang       2016-06-06  338  	dma_free_coherent(priv->dev,
5b8aad93c52bdda Holger Brunck    2017-05-17  339  			  RX_BD_RING_LEN * sizeof(struct qe_bd),
c19b6d246a35627 Zhao Qiang       2016-06-06  340  			  priv->rx_bd_base, priv->dma_rx_bd);
1efb597d8bf56cb Zhao Qiang       2016-07-15  341  free_uccf:
c19b6d246a35627 Zhao Qiang       2016-06-06  342  	ucc_fast_free(priv->uccf);
c19b6d246a35627 Zhao Qiang       2016-06-06  343  
c19b6d246a35627 Zhao Qiang       2016-06-06  344  	return ret;
c19b6d246a35627 Zhao Qiang       2016-06-06  345  }
c19b6d246a35627 Zhao Qiang       2016-06-06  346  

:::::: The code at line 305 was first introduced by commit
:::::: c19b6d246a35627c3a69b2fa6bdece212b48214b drivers/net: support hdlc function for QE-UCC

:::::: TO: Zhao Qiang <qiang.zhao@....com>
:::::: CC: David S. Miller <davem@...emloft.net>

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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