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Date:   Wed, 30 Dec 2020 17:51:29 +0200
From:   Iskren Chernev <iskren.chernev@...il.com>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>
Cc:     Andy Gross <agross@...nel.org>, Rob Herring <robh+dt@...nel.org>,
        linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Iskren Chernev <iskren.chernev@...il.com>,
        ~postmarketos/upstreaming@...ts.sr.ht,
        Brian Masney <masneyb@...tation.org>
Subject: [PATCH 1/4] ARM: dts: qcom: msm8974: add gpu support

From: Brian Masney <masneyb@...tation.org>

Add support for the a3xx GPU

Signed-off-by: Brian Masney <masneyb@...tation.org>
---
 arch/arm/boot/dts/qcom-msm8974.dtsi | 45 +++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 51f5f904f9eb9..c399446d8154e 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1399,6 +1399,51 @@ cnoc: interconnect@...80000 {
 			         <&rpmcc RPM_SMD_CNOC_A_CLK>;
 		};
 
+		gpu_opp_table: opp_table {
+			status = "disabled";
+
+			compatible = "operating-points-v2";
+
+			opp-800000000 {
+				opp-hz = /bits/ 64 <800000000>;
+			};
+
+			opp-500000000 {
+				opp-hz = /bits/ 64 <500000000>;
+			};
+
+			opp-275000000 {
+				opp-hz = /bits/ 64 <275000000>;
+			};
+		};
+
+		gpu: adreno@...00000 {
+			status = "disabled";
+
+			compatible = "qcom,adreno-330.2",
+			             "qcom,adreno";
+			reg = <0xfdb00000 0x10000>;
+			reg-names = "kgsl_3d0_reg_memory";
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "kgsl_3d0_irq";
+			clock-names = "core",
+			              "iface",
+			              "mem_iface";
+			clocks = <&mmcc OXILI_GFX3D_CLK>,
+			         <&mmcc OXILICX_AHB_CLK>,
+			         <&mmcc OXILICX_AXI_CLK>;
+			sram = <&gmu_sram>;
+			power-domains = <&mmcc OXILICX_GDSC>;
+			operating-points-v2 = <&gpu_opp_table>;
+
+			interconnects = <&mmssnoc MNOC_MAS_GRAPHICS_3D &bimc BIMC_SLV_EBI_CH0>,
+			                <&ocmemnoc OCMEM_VNOC_MAS_GFX3D &ocmemnoc OCMEM_SLV_OCMEM>;
+			interconnect-names = "gfx-mem",
+			                     "ocmem";
+
+			// iommus = <&gpu_iommu 0>;
+		};
+
 		mdss: mdss@...00000 {
 			status = "disabled";
 

base-commit: d7a03a44a5e93f39ece70ec75d25c6088caa0fdb
prerequisite-patch-id: aba6f684932cab35d98457c21e4ff7a5ac75c753
prerequisite-patch-id: 4884d57df1bd197896b69e115d9002d6c26ae2e2
prerequisite-patch-id: 4f1aba3c3675236b18578eedbe71b0cdca01ed77
prerequisite-patch-id: cbfe6ccfebb142370baff15bbdf3cf2f34ee77df
-- 
2.29.2

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