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Message-Id: <907e6379ae5fc8f5decdb344485123425de7afc1.1609306622.git.vijayakannan.ayyathurai@intel.com>
Date: Wed, 30 Dec 2020 14:25:26 +0800
From: vijayakannan.ayyathurai@...el.com
To: daniel.lezcano@...aro.org, tglx@...utronix.de, robh+dt@...nel.org,
catalin.marinas@....com, will@...nel.org
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
andriy.shevchenko@...ux.intel.com, mgross@...ux.intel.com,
wan.ahmad.zainie.wan.mohamad@...el.com,
lakshmi.bai.raja.subramanian@...el.com, chen.yong.seow@...el.com,
vijayakannan.ayyathurai@...el.com
Subject: [PATCH v2 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC timer
From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@...el.com>
Add Device Tree bindings for the Timer IP, which used as clocksource and
clockevent device in the Intel Keem Bay SoC.
Acked-by: Mark Gross <mgross@...ux.intel.com>
Acked-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@...el.com>
---
.../bindings/timer/intel,keembay-timer.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
new file mode 100644
index 000000000000..197493336ac2
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Keem Bay SoC Timers
+
+maintainers:
+ - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@...el.com>
+ - Vijayakannan Ayyathurai <vijayakannan.ayyathurai@...el.com>
+
+description:
+ Intel Keem Bay SoC Timers block contains 8 32-bit general purpose timers,
+ a free running 64-bit counter, a random number generator and a watchdog
+ timer. Each gpt can generate an individual interrupt.
+
+properties:
+ compatible:
+ enum:
+ - intel,keembay-timer
+
+ reg:
+ maxItems: 3
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #define KEEM_BAY_A53_TIM
+
+ timer@...30010 {
+ compatible = "intel,keembay-timer";
+ reg = <0x20330010 0xc>,
+ <0x203300e8 0xc>,
+ <0x20331000 0xc>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.17.1
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