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Date:   Thu, 31 Dec 2020 08:33:15 +0800
From:   Huacai Chen <chenhuacai@...nel.org>
To:     Jiaxun Yang <jiaxun.yang@...goat.com>
Cc:     "open list:MIPS" <linux-mips@...r.kernel.org>,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        WANG Xuerui <git@...0n.name>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Serge Semin <Sergey.Semin@...kalelectronics.ru>,
        周琰杰 (Zhou Yanjie) 
        <zhouyanjie@...yeetech.com>, Paul Cercueil <paul@...pouillou.net>,
        Tiezhu Yang <yangtiezhu@...ngson.cn>,
        YunQiang Su <syq@...ian.org>,
        Liangliang Huang <huanglllzu@...il.com>,
        LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/3] MIPS: cpu-probe: Vulnerabilities for Loongson cores

Hi, Jiaxun,

On Wed, Dec 30, 2020 at 11:26 AM Jiaxun Yang <jiaxun.yang@...goat.com> wrote:
>
> Loongson64C is known to be vulnerable to meltdown according to
> PoC from Rui Wang <r@....cc>.
How about Loongson-3A1000/3B1500, and Loongson-2E/2F?

Huacai
>
> Loongson64G defended these side-channel attack by silicon.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@...goat.com>
> ---
>  arch/mips/kernel/cpu-probe.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
> index 2460783dbdb1..24b21f51353c 100644
> --- a/arch/mips/kernel/cpu-probe.c
> +++ b/arch/mips/kernel/cpu-probe.c
> @@ -2092,6 +2092,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
>                 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
>                         MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
>                 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
> +               c->vulnerabilities |= MIPS_VULNBL_MELTDOWN;
> +               c->vulnerable |= MIPS_VULNBL_MELTDOWN;
>                 break;
>         case PRID_IMP_LOONGSON_64G:
>                 c->cputype = CPU_LOONGSON64;
> @@ -2100,6 +2102,8 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
>                 set_isa(c, MIPS_CPU_ISA_M64R2);
>                 decode_cpucfg(c);
>                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
> +               c->vulnerabilities |= MIPS_VULNBL_MELTDOWN |
> +                             MIPS_VULNBL_SPECTRE_V1 | MIPS_VULNBL_SPECTRE_V2;
>                 break;
>         default:
>                 panic("Unknown Loongson Processor ID!");
> --
> 2.30.0
>

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