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Message-ID: <1609757093-30618-1-git-send-email-weiyi.lu@mediatek.com>
Date:   Mon, 4 Jan 2021 18:44:51 +0800
From:   Weiyi Lu <weiyi.lu@...iatek.com>
To:     Enric Balletbo Serra <eballetbo@...il.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Nicolas Boichat <drinkcat@...omium.org>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-mediatek@...ts.infradead.org>,
        <srv_heupstream@...iatek.com>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        Weiyi Lu <weiyi.lu@...iatek.com>
Subject: [PATCH 0/2] Fixes for new SCPSYS power domains controller driver

This patch is base on v5.10-rc1 and
series "Add new driver for SCPSYS power domains controller"[1]

[1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013

Weiyi Lu (2):
  soc: mediatek: Add regulator control for MT8192 MFG power domain
  soc: mediatek: Fix the clock prepared issue

 drivers/soc/mediatek/mt8192-pm-domains.h |  1 +
 drivers/soc/mediatek/mtk-pm-domains.c    | 73 ++++++++++++++++--------
 drivers/soc/mediatek/mtk-pm-domains.h    |  2 +
 3 files changed, 51 insertions(+), 25 deletions(-)

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