linux-kernel - Re: [PATCH V2] mtd: rawnand: qcom: update last code word register

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Message-ID: <20210105143157.6262f7d5@xps13>
Date:   Tue, 5 Jan 2021 14:31:57 +0100
From:   Miquel Raynal <miquel.raynal@...tlin.com>
To:     Md Sadre Alam <mdalam@...eaurora.org>
Cc:     manivannan.sadhasivam@...aro.org, linux-mtd@...ts.infradead.org,
        linux-kernel@...r.kernel.org, boris.brezillon@...labora.com,
        vigneshr@...com, sricharan@...eaurora.org
Subject: Re: [PATCH V2] mtd: rawnand: qcom: update last code word register

Hello,

Md Sadre Alam <mdalam@...eaurora.org> wrote on Tue,  5 Jan 2021
00:01:18 +0530:

> From QPIC version 2.0 onwards new register got added to
> read last codeword. This change will update the same.
> 
> For first three code word READ_LOCATION_n register will be
> use.For last code wrod READ_LOCATION_LAST_CW_n register will be

s/wrod/word

> use.
> 

Please add a Fixes tag here

> Signed-off-by: Md Sadre Alam <mdalam@...eaurora.org>
> ---
> [V2]
>  * Fixed alignment for NAND_READ_LOCATION_LAST_CW_n reg macro
>  * Changed number of register write to 1 when NAND_READ_LOCATION_LAST_CW_n register will use
>  drivers/mtd/nand/raw/qcom_nandc.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index eaef51d..9e89236 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -48,10 +48,10 @@
>  #define	NAND_READ_LOCATION_1		0xf24
>  #define	NAND_READ_LOCATION_2		0xf28
>  #define	NAND_READ_LOCATION_3		0xf2c
> -#define NAND_READ_LOCATION_LAST_CW_0    0xf40
> -#define NAND_READ_LOCATION_LAST_CW_1    0xf44
> -#define NAND_READ_LOCATION_LAST_CW_2    0xf48
> -#define NAND_READ_LOCATION_LAST_CW_3    0xf4c
> +#define	NAND_READ_LOCATION_LAST_CW_0	0xf40
> +#define	NAND_READ_LOCATION_LAST_CW_1	0xf44
> +#define	NAND_READ_LOCATION_LAST_CW_2	0xf48
> +#define	NAND_READ_LOCATION_LAST_CW_3	0xf4c

It looks like you forgot to squash this to you original patch :)

>  
>  /* dummy register offsets, used by write_reg_dma */
>  #define	NAND_DEV_CMD1_RESTORE		0xdead
> @@ -1125,7 +1125,7 @@ config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
>  	if (nandc->props->is_bam) {
>  		if (nandc->props->qpic_v2)
>  			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0,
> -				      4, NAND_BAM_NEXT_SGL);
> +				      1, NAND_BAM_NEXT_SGL);
>  		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>  			      NAND_BAM_NEXT_SGL);
>  	}

Thanks,
Miquèl