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Message-ID: <20210106055939.19386-4-chiawei_wang@aspeedtech.com>
Date: Wed, 6 Jan 2021 13:59:36 +0800
From: "Chia-Wei, Wang" <chiawei_wang@...eedtech.com>
To: <robh+dt@...nel.org>, <joel@....id.au>, <andrew@...id.au>,
<tglx@...utronix.de>, <maz@...nel.org>, <p.zabel@...gutronix.de>,
<linux-aspeed@...ts.ozlabs.org>, <openbmc@...ts.ozlabs.org>,
<devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
CC: <BMC-SW@...eedtech.com>
Subject: [PATCH 3/6] clk: ast2600: Add eSPI reset bit
Add bit field definition for the eSPI reset control.
Signed-off-by: Chia-Wei, Wang <chiawei_wang@...eedtech.com>
---
include/dt-bindings/clock/ast2600-clock.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
index 62b9520a00fd..964934b1caef 100644
--- a/include/dt-bindings/clock/ast2600-clock.h
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -89,6 +89,7 @@
#define ASPEED_CLK_MAC4RCLK 70
/* Only list resets here that are not part of a gate */
+#define ASPEED_RESET_ESPI 57
#define ASPEED_RESET_ADC 55
#define ASPEED_RESET_JTAG_MASTER2 54
#define ASPEED_RESET_I3C_DMA 39
--
2.17.1
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