| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAATdQgBJ7EVRJW7iJG63yW89fh5skpe9-UCd4pdZystV_JrvCg@mail.gmail.com>
Date: Wed, 6 Jan 2021 18:52:45 +0800
From: Ikjoon Jang <ikjn@...omium.org>
To: Weiyi Lu <weiyi.lu@...iatek.com>
Cc: Rob Herring <robh@...nel.org>,
Nicolas Boichat <drinkcat@...omium.org>,
srv_heupstream <srv_heupstream@...iatek.com>,
Stephen Boyd <sboyd@...nel.org>,
open list <linux-kernel@...r.kernel.org>,
Project_Global_Chrome_Upstream_Group@...iatek.com,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
Matthias Brugger <matthias.bgg@...il.com>,
linux-clk@...r.kernel.org
Subject: Re: [PATCH v6 10/22] clk: mediatek: Add MT8192 basic clocks support
On Wed, Jan 6, 2021 at 6:42 PM Weiyi Lu <weiyi.lu@...iatek.com> wrote:
>
> On Wed, 2021-01-06 at 18:25 +0800, Ikjoon Jang wrote:
> > On Tue, Dec 22, 2020 at 9:14 PM Weiyi Lu <weiyi.lu@...iatek.com> wrote:
> > >
> > > Add MT8192 basic clock providers, include topckgen, apmixedsys,
> > > infracfg and pericfg.
> > >
> > > Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
> > > ---
> > > drivers/clk/mediatek/Kconfig | 8 +
> > > drivers/clk/mediatek/Makefile | 1 +
> > > drivers/clk/mediatek/clk-mt8192.c | 1326 +++++++++++++++++++++++++++++++++++++
> > > drivers/clk/mediatek/clk-mux.h | 15 +
> > > 4 files changed, 1350 insertions(+)
> > > create mode 100644 drivers/clk/mediatek/clk-mt8192.c
> > >
> >
> > <snip>
> >
> > > diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
> > > index f5625f4..afbc7df 100644
> > > --- a/drivers/clk/mediatek/clk-mux.h
> > > +++ b/drivers/clk/mediatek/clk-mux.h
> > > @@ -77,6 +77,21 @@ struct mtk_mux {
> > > _width, _gate, _upd_ofs, _upd, \
> > > CLK_SET_RATE_PARENT)
> > >
> > > +#define MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> > > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> > > + _upd_ofs, _upd, _flags) \
> > > + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> > > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> > > + 0, _upd_ofs, _upd, _flags, \
> > > + mtk_mux_clr_set_upd_ops)
> > > +
> > > +#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
> > > + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> > > + _upd_ofs, _upd) \
> > > + MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
> > > + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
> > > + _width, _upd_ofs, _upd, CLK_SET_RATE_PARENT)
> > > +
> >
> > conflicts, these macros are already existed in upstream.
>
> really? These two macros don't show up in 5.11-rc1 yet.
yep, maybe this one: a3ae549917f1 "clk: mediatek: Add new clkmux register API"
>
> > > struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
> > > struct regmap *regmap,
> > > spinlock_t *lock);
> > > --
> > > 1.8.1.1.dirty
> > > _______________________________________________
> > > Linux-mediatek mailing list
> > > Linux-mediatek@...ts.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Powered by blists - more mailing lists