linux-kernel - [PATCH v1 2/3] x86/cpu: Set low performance CRC32C flag on some Zhaoxin CPUs

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Date:   Thu, 7 Jan 2021 14:19:07 +0800
From:   Tony W Wang-oc <TonyWWang-oc@...oxin.com>
To:     <herbert@...dor.apana.org.au>, <davem@...emloft.net>,
        <tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>,
        <x86@...nel.org>, <hpa@...or.com>, <tony.luck@...el.com>,
        <dave.hansen@...el.com>, <seanjc@...gle.com>,
        <fenghua.yu@...el.com>, <thomas.lendacky@....com>,
        <kyung.min.park@...el.com>, <kim.phillips@....com>,
        <mgross@...ux.intel.com>, <peterz@...radead.org>,
        <krish.sadhukhan@...cle.com>, <liam.merwick@...cle.com>,
        <mlevitsk@...hat.com>, <reinette.chatre@...el.com>,
        <babu.moger@....com>, <linux-crypto@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
CC:     <TimGuo-oc@...oxin.com>, <CooperYan@...oxin.com>,
        <QiyuanWang@...oxin.com>, <HerryYang@...oxin.com>,
        <CobeChen@...oxin.com>, <SilviaZhao@...oxin.com>
Subject: [PATCH v1 2/3] x86/cpu: Set low performance CRC32C flag on some Zhaoxin CPUs

Some Zhaoxin CPUs declare support SSE4.2 instruction sets but
having a CRC32C instruction implementation that not working as
intended. Set low performance CRC32C flag on these CPUs for later
use.

Signed-off-by: Tony W Wang-oc <TonyWWang-oc@...oxin.com>
---
 arch/x86/kernel/cpu/centaur.c | 7 +++++++
 arch/x86/kernel/cpu/zhaoxin.c | 6 ++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 345f7d9..13e6fbe 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -109,6 +109,13 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 	}
+
+	/*
+	 * These CPUs declare support SSE4.2 instruction sets but
+	 * having low performance CRC32C instruction implementation.
+	 */
+	if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
+		set_cpu_cap(c, X86_FEATURE_CRC32C);
 }
 
 static void init_centaur(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 05fa4ef..837ec65 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -79,6 +79,12 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c)
 			c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
 	}
 
+	/*
+	 * These CPUs declare support SSE4.2 instruction sets but
+	 * having low performance CRC32C instruction implementation.
+	 */
+	if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
+		set_cpu_cap(c, X86_FEATURE_CRC32C);
 }
 
 static void init_zhaoxin(struct cpuinfo_x86 *c)
-- 
2.7.4