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Date: Thu, 7 Jan 2021 10:43:50 +0800 From: Roger Lu <roger.lu@...iatek.com> To: Matthias Brugger <matthias.bgg@...il.com>, Enric Balletbo Serra <eballetbo@...il.com>, Kevin Hilman <khilman@...nel.org>, Rob Herring <robh+dt@...nel.org>, Nicolas Boichat <drinkcat@...gle.com>, Stephen Boyd <sboyd@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de> CC: Fan Chen <fan.chen@...iatek.com>, HenryC Chen <HenryC.Chen@...iatek.com>, YT Lee <yt.lee@...iatek.com>, Xiaoqing Liu <Xiaoqing.Liu@...iatek.com>, Charles Yang <Charles.Yang@...iatek.com>, Angus Lin <Angus.Lin@...iatek.com>, Mark Rutland <mark.rutland@....com>, Nishanth Menon <nm@...com>, Roger Lu <roger.lu@...iatek.com>, <devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <linux-pm@...r.kernel.org> Subject: [PATCH v11 1/7] dt-bindings: soc: mediatek: add mtk svs dt-bindings Document the binding for enabling mtk svs on MediaTek SoC. Signed-off-by: Roger Lu <roger.lu@...iatek.com> --- .../bindings/soc/mediatek/mtk-svs.yaml | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml new file mode 100644 index 000000000000..bb8c345a0c0a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mtk-svs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Introduce MTK SVS engine + +maintainers: + - Matthias Brugger <matthias.bgg@...il.com> + - Kevin Hilman <khilman@...nel.org> + - Nishanth Menon <nm@...com> + +description: |+ + The Smart Voltage Scaling(SVS) engine is a piece of hardware + which has several controllers(banks) for calculating suitable + voltage to different power domains(CPU/GPU/CCI) according to + chip process corner, temperatures and other factors. Then DVFS + driver could apply SVS bank voltage to PMIC/Buck. + +properties: + compatible: + enum: + - mediatek,mt8183-svs + + reg: + description: Address range of the MTK SVS controller. + maxItems: 1 + + interrupts: + description: IRQ for the MTK SVS controller. + maxItems: 1 + + clocks: + description: Main clock for MTK SVS controller to work. + + clock-names: + const: main + + nvmem-cells: + maxItems: 2 + description: + Phandle to the calibration data provided by a nvmem device. + + nvmem-cell-names: + items: + - const: svs-calibration-data + - const: t-calibration-data + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + svs@...0b000 { + compatible = "mediatek,mt8183-svs"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; + clocks = <&infracfg CLK_INFRA_THERM>; + clock-names = "main"; + nvmem-cells = <&svs_calibration>, <&thermal_calibration>; + nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; + }; + }; -- 2.18.0
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