linux-kernel - [PATCH v7 2/5] PCI: dwc: add support to handle ZRX-DC Compliant PHYs

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Message-Id: <1610033323-10560-3-git-send-email-shradha.t@samsung.com>
Date:   Thu,  7 Jan 2021 20:58:40 +0530
From:   Shradha Todi <shradha.t@...sung.com>
To:     linux-kernel@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-pci@...r.kernel.org
Cc:     pankaj.dubey@...sung.com, sriram.dash@...sung.com,
        niyas.ahmed@...sung.com, p.rajanbabu@...sung.com,
        l.mehra@...sung.com, hari.tv@...sung.com,
        Anvesh Salveru <anvesh.salveru@...il.com>,
        Shradha Todi <shradha.t@...sung.com>,
        Jingoo Han <jingoohan1@...il.com>,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Rob Herring <robh@...nel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>
Subject: [PATCH v7 2/5] PCI: dwc: add support to handle ZRX-DC Compliant
 PHYs

From: Pankaj Dubey <pankaj.dubey@...sung.com>

Many platforms use DesignWare controller but the PHY can be different in
different platforms. If the PHY is compliant is to ZRX-DC specification it
helps in low power consumption during power states.

If current data rate is 8.0 GT/s or higher and PHY is not compliant to
ZRX-DC specification, then after every 100ms link should transition to
recovery state during the low power states.

DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in
GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY.

Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant variable to
specify this property to the controller.

Signed-off-by: Anvesh Salveru <anvesh.salveru@...il.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@...sung.com>
Signed-off-by: Shradha Todi <shradha.t@...sung.com>
Cc: Jingoo Han <jingoohan1@...il.com>
Cc: Gustavo Pimentel <gustavo.pimentel@...opsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
Cc: Rob Herring <robh@...nel.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>
---
 drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++
 drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 645fa18..74590c7 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -722,4 +722,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
 		       PCIE_PL_CHK_REG_CHK_REG_START;
 		dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
 	}
+
+	if (pci->phy_zrxdc_compliant) {
+		val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED);
+		val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL;
+		dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val);
+	}
 }
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 0207840..8b905a2 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -74,6 +74,9 @@
 #define PCIE_MSI_INTR0_MASK		0x82C
 #define PCIE_MSI_INTR0_STATUS		0x830
 
+#define PCIE_PORT_GEN3_RELATED		0x890
+#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL	BIT(0)
+
 #define PCIE_PORT_MULTI_LANE_CTRL	0x8C0
 #define PORT_MLTI_UPCFG_SUPPORT		BIT(7)
 
@@ -273,6 +276,7 @@ struct dw_pcie {
 	u8			n_fts[2];
 	bool			iatu_unroll_enabled: 1;
 	bool			io_cfg_atu_shared: 1;
+	bool			phy_zrxdc_compliant;
 };
 
 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
-- 
2.7.4