linux-kernel - [PATCH v7 5/5] arm64: tegra: Add support for ZRX DC PHY property

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Message-Id: <1610033323-10560-6-git-send-email-shradha.t@samsung.com>
Date:   Thu,  7 Jan 2021 20:58:43 +0530
From:   Shradha Todi <shradha.t@...sung.com>
To:     linux-kernel@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-pci@...r.kernel.org
Cc:     pankaj.dubey@...sung.com, sriram.dash@...sung.com,
        niyas.ahmed@...sung.com, p.rajanbabu@...sung.com,
        l.mehra@...sung.com, hari.tv@...sung.com,
        Shradha Todi <shradha.t@...sung.com>,
        Rob Herring <robh+dt@...nel.org>,
        Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Vidya Sagar <vidyas@...dia.com>
Subject: [PATCH v7 5/5] arm64: tegra: Add support for ZRX DC PHY property

DesignWare controller driver provides the support to handle the PHYs which
are compliant to ZRX-DC specification based on "phy-zrxdc-compliant" DT
property. So, add "phy-zrxdc-compliant" property in tegra PCIe PHY DT
nodes.

Signed-off-by: Pankaj Dubey <pankaj.dubey@...sung.com>
Signed-off-by: Shradha Todi <shradha.t@...sung.com>
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Thierry Reding <thierry.reding@...il.com>
Cc: Jonathan Hunter <jonathanh@...dia.com>
Cc: Vidya Sagar <vidyas@...dia.com>
To: devicetree@...r.kernel.org
To: linux-tegra@...r.kernel.org
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 25f36d6..9d91006 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1006,6 +1006,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_1: phy@...0000 {
@@ -1014,6 +1015,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_2: phy@...0000 {
@@ -1022,6 +1024,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_3: phy@...0000 {
@@ -1030,6 +1033,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_4: phy@...0000 {
@@ -1038,6 +1042,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_5: phy@...0000 {
@@ -1046,6 +1051,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_6: phy@...0000 {
@@ -1054,6 +1060,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_7: phy@...0000 {
@@ -1062,6 +1069,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_8: phy@...0000 {
@@ -1070,6 +1078,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_9: phy@...0000 {
@@ -1078,6 +1087,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_0: phy@...0000 {
@@ -1086,6 +1096,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_1: phy@...0000 {
@@ -1094,6 +1105,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_2: phy@...0000 {
@@ -1102,6 +1114,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_3: phy@...0000 {
@@ -1110,6 +1123,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_4: phy@...0000 {
@@ -1118,6 +1132,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_5: phy@...0000 {
@@ -1126,6 +1141,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_6: phy@...0000 {
@@ -1134,6 +1150,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_nvhs_7: phy@...0000 {
@@ -1142,6 +1159,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_10: phy@...0000 {
@@ -1150,6 +1168,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		p2u_hsio_11: phy@...0000 {
@@ -1158,6 +1177,7 @@
 			reg-names = "ctl";
 
 			#phy-cells = <0>;
+			phy-zrxdc-compliant;
 		};
 
 		hsp_aon: hsp@...0000 {
-- 
2.7.4