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Message-ID: <HK0PR06MB3380BD8A5BB1B1E7CB466C9BF2AE0@HK0PR06MB3380.apcprd06.prod.outlook.com>
Date: Fri, 8 Jan 2021 03:09:40 +0000
From: Ryan Chen <ryan_chen@...eedtech.com>
To: Joel Stanley <joel@....id.au>,
ChiaWei Wang <chiawei_wang@...eedtech.com>,
Jeremy Kerr <jk@...econstruct.com.au>
CC: Rob Herring <robh@...nel.org>, "andrew@...id.au" <andrew@...id.au>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"maz@...nel.org" <maz@...nel.org>,
"p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
"linux-aspeed@...ts.ozlabs.org" <linux-aspeed@...ts.ozlabs.org>,
"openbmc@...ts.ozlabs.org" <openbmc@...ts.ozlabs.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
BMC-SW <BMC-SW@...eedtech.com>
Subject: RE: [PATCH 5/6] soc: aspeed: Add eSPI driver
> -----Original Message-----
> From: Joel Stanley <joel@....id.au>
> Sent: Friday, January 8, 2021 10:59 AM
> To: ChiaWei Wang <chiawei_wang@...eedtech.com>; Jeremy Kerr
> <jk@...econstruct.com.au>
> Cc: Rob Herring <robh@...nel.org>; andrew@...id.au; tglx@...utronix.de;
> maz@...nel.org; p.zabel@...gutronix.de; linux-aspeed@...ts.ozlabs.org;
> openbmc@...ts.ozlabs.org; devicetree@...r.kernel.org;
> linux-arm-kernel@...ts.infradead.org; linux-kernel@...r.kernel.org; BMC-SW
> <BMC-SW@...eedtech.com>
> Subject: Re: [PATCH 5/6] soc: aspeed: Add eSPI driver
>
> On Thu, 7 Jan 2021 at 02:39, ChiaWei Wang
> <chiawei_wang@...eedtech.com> wrote:
> >
> > Hi Rob,
> >
> > > -----Original Message-----
> > > From: Rob Herring <robh@...nel.org>
> > > Sent: Wednesday, January 6, 2021 11:32 PM
> > > To: ChiaWei Wang <chiawei_wang@...eedtech.com>
> > > Subject: Re: [PATCH 5/6] soc: aspeed: Add eSPI driver
> > >
> > > On Wed, Jan 06, 2021 at 01:59:38PM +0800, Chia-Wei, Wang wrote:
> > > > The Aspeed eSPI controller is slave device to communicate with the
> > > > master through the Enhanced Serial Peripheral Interface (eSPI).
> > > > All of the four eSPI channels, namely peripheral, virtual wire,
> > > > out-of-band, and flash are supported.
> > > >
> > > > Signed-off-by: Chia-Wei, Wang <chiawei_wang@...eedtech.com>
> > > > ---
> > > > drivers/soc/aspeed/Kconfig | 49 ++
> > > > drivers/soc/aspeed/Makefile | 5 +
> > > > drivers/soc/aspeed/aspeed-espi-ctrl.c | 197 ++++++
> > > > drivers/soc/aspeed/aspeed-espi-flash.c | 490 ++++++++++++++
> > > > drivers/soc/aspeed/aspeed-espi-oob.c | 706
> > > ++++++++++++++++++++
> > > > drivers/soc/aspeed/aspeed-espi-peripheral.c | 613
> +++++++++++++++++
> > > > drivers/soc/aspeed/aspeed-espi-vw.c | 211 ++++++
> > > > include/uapi/linux/aspeed-espi.h | 160 +++++
> > > > 8 files changed, 2431 insertions(+) create mode 100644
> > > > drivers/soc/aspeed/aspeed-espi-ctrl.c
> > > > create mode 100644 drivers/soc/aspeed/aspeed-espi-flash.c
> > > > create mode 100644 drivers/soc/aspeed/aspeed-espi-oob.c
> > > > create mode 100644 drivers/soc/aspeed/aspeed-espi-peripheral.c
> > > > create mode 100644 drivers/soc/aspeed/aspeed-espi-vw.c
> > >
> > > drivers/spi/ is the correct location for a SPI controller.
> > >
> > > > create mode 100644 include/uapi/linux/aspeed-espi.h
> > >
> > > This userspace interface is not going to be accepted upstream.
> > >
> > > I'd suggest you look at similar SPI flash capable SPI controller
> > > drivers upstream and model your driver after them. This looks like it needs
> major reworking.
> > >
> > eSPI resues the timing and electrical specification of SPI but runs completely
> different protocol.
> > Only the flash channel is related to SPI and the other 3 channels are for
> EC/BMC/SIO.
> > Therefore, an eSPI driver might not fit into the SPI model.
>
> I agree, the naming is confusing but eSPI doesn't belong in drivers/spi.
>
> As it is a bus that is common to more than just the Aspeed BMC, we may want
> to implement it as a new bus type that has devices hanging off it, similar to
> FSI.
>
The ASPEED eSPI controller driver is slave side device, not master side. I think it will be stay soc/aspeed first.
Because is most SoC Chip related.
Cheers,
Ryan
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