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Date: Fri, 8 Jan 2021 13:04:27 +0100 From: Robert Foss <robert.foss@...aro.org> To: agross@...nel.org, bjorn.andersson@...aro.org, robert.foss@...aro.org, todor.too@...il.com, mchehab@...nel.org, robh+dt@...nel.org, catalin.marinas@....com, will@...nel.org, shawnguo@...nel.org, leoyang.li@....com, geert+renesas@...der.be, arnd@...db.de, Anson.Huang@....com, michael@...le.cc, agx@...xcpu.org, max.oss.09@...il.com, linux-arm-msm@...r.kernel.org, linux-media@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, AngeloGioacchino Del Regno <kholk11@...il.com>, Andrey Konovalov <andrey.konovalov@...aro.org> Cc: Tomasz Figa <tfiga@...omium.org>, Azam Sadiq Pasha Kapatrala Syed <akapatra@...cinc.com>, Sarvesh Sridutt <Sarvesh.Sridutt@...rtwirelesscompute.com>, Laurent Pinchart <laurent.pinchart@...asonboard.com> Subject: [PATCH v1 15/17] arm64: dts: sdm845: Add CAMSS ISP node Add the camss dt node for sdm845. Signed-off-by: Robert Foss <robert.foss@...aro.org> --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 151 +++++++++++++++++++++++++++ 1 file changed, 151 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index bcf888381f14..286d50fcd9a5 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3911,6 +3911,157 @@ videocc: clock-controller@...0000 { #reset-cells = <1>; }; + camss: camss@...000 { + compatible = "qcom,sdm845-camss"; + reg = <0 0xac65000 0 0x1000>, + <0 0xac66000 0 0x1000>, + <0 0xac67000 0 0x1000>, + <0 0xac68000 0 0x1000>, + <0 0xacb3000 0 0x1000>, + <0 0xacba000 0 0x1000>, + <0 0xacc8000 0 0x1000>, + <0 0xacaf000 0 0x4000>, + <0 0xacb6000 0 0x4000>, + <0 0xacc4000 0 0x4000>; + reg-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csid0", + "csid1", + "csid2", + "vfe0", + "vfe1", + "vfe_lite"; + interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csid0", + "csid1", + "csid2", + "vfe0", + "vfe1", + "vfe_lite"; + power-domains = <&clock_camcc IFE_0_GDSC>, + <&clock_camcc IFE_1_GDSC>, + <&clock_camcc TITAN_TOP_GDSC>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_SOC_AHB_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>; + clock-names = "gcc_camera_ahb", + "gcc_camera_axi", + "camnoc_axi", + "cpas_ahb", + "slow_ahb_src", + "soc_ahb", + "cphy_rx_src", + "csiphy0", + "csiphy0_timer_src", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer_src", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer_src", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer_src", + "csiphy3_timer", + "vfe0_axi", + "vfe0", + "vfe0_src", + "vfe0_cphy_rx", + "csi0", /* renamed to fit naming-scheme of older hardware */ + "csi0_src", /* renamed to fit naming-scheme of older hardware */ + "vfe1_axi", + "vfe1", + "vfe1_src", + "vfe1_cphy_rx", + "csi1", /* renamed to fit naming-scheme of older hardware */ + "csi1_src", /* renamed to fit naming-scheme of older hardware */ + "vfe_lite", + "vfe_lite_src", + "vfe_lite_cphy_rx", + "csi2", /* renamed to fit naming-scheme of older hardware */ + "csi2_src"; /* renamed to fit naming-scheme of older hardware */ + + iommus = <&apps_smmu 0x0808 0x0>, + <&apps_smmu 0x0810 0x8>, + <&apps_smmu 0x0c08 0x0>, + <&apps_smmu 0x0c10 0x8>; + status = "disabled"; + + interconnects = + <&gladiator_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>, + <&mmss_noc MASTER_CAMNOC_HF0 + &mmss_noc SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_HF0_UNCOMP + &mmss_noc SLAVE_CAMNOC_UNCOMP>, + <&mmss_noc MASTER_CAMNOC_HF1 + &mmss_noc SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_HF1_UNCOMP + &mmss_noc SLAVE_CAMNOC_UNCOMP>, + <&mmss_noc MASTER_CAMNOC_SF + &mmss_noc SLAVE_EBI1>, + <&mmss_noc MASTER_CAMNOC_SF_UNCOMP + &mmss_noc SLAVE_CAMNOC_UNCOMP>; + interconnect-names = "cam_ahb", + "hf_1_mnoc", "hf_1_camnoc", + "hf_2_mnoc", "hf_2_camnoc", + "sf_1_mnoc", "sf_1_camnoc"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + cci: cci@...a000 { compatible = "qcom,sdm845-cci"; #address-cells = <1>; -- 2.27.0
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