linux-kernel - Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

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Message-ID: <fa091855-8096-6377-e173-ce1cd02f74ec@somainline.org>
Date:   Fri, 8 Jan 2021 14:39:51 +0100
From:   Konrad Dybcio <konrad.dybcio@...ainline.org>
To:     Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>,
        robdclark@...il.com
Cc:     airlied@...ux.ie, airlied@...hat.com, akhilpo@...eaurora.org,
        angelogioacchino.delregno@...ainline.org,
        bjorn.andersson@...aro.org, daniel@...ll.ch,
        dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
        jcrouse@...eaurora.org, jonathan@...ek.ca,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        marijn.suijten@...ainline.org, martin.botka@...ainline.org,
        phone-devel@...r.kernel.org, sean@...rly.run, shawn.guo@...aro.org,
        smasetty@...eaurora.org, ~postmarketos/upstreaming@...ts.sr.ht
Subject: Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx

> Konrad, can you please test this below change without your change?

This brings no difference, a BUG still happens. We're still calling to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330 into an A640..

Also, relying on disabling LLCC in the config is out of question as it makes the arm32 kernel not compile with DRM/MSM and it just removes the functionality on devices with a6xx.. (unless somebody removes the dependency on it, which in my opinion is even worse and will cause more problems for developers!).

The bigger question is how and why did that piece of code ever make it to adreno_gpu.c and not a6xx_gpu.c?

To solve it in a cleaner way I propose to move it to an a6xx-specific file, or if it's going to be used with next-gen GPUs, perhaps manage calling of this code via an adreno quirk/feature in adreno_device.c. Now that I think about it, A5xx GPMU en/disable could probably managed like that, instead of using tons of if-statements for each GPU model that has it..

While we're at it, do ALL (and I truly do mean ALL, including the low-end ones, this will be important later on) A6xx GPUs make use of that feature?

Konrad