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Message-ID: <ea422151-b4df-f7d3-c695-b4ebcb251307@nvidia.com>
Date:   Fri, 8 Jan 2021 20:43:16 +0530
From:   Sameer Pujar <spujar@...dia.com>
To:     Peter Geis <pgwipeout@...il.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        "Peter De Schrijver" <pdeschrijver@...dia.com>,
        Prashant Gaikwad <pgaikwad@...dia.com>,
        Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        Jaroslav Kysela <perex@...ex.cz>,
        Takashi Iwai <tiwai@...e.com>, Mohan Kumar <mkumard@...dia.com>
CC:     <linux-clk@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <alsa-devel@...a-project.org>,
        Ion Agorria <ion@...rria.com>
Subject: Re: [PATCH v2 1/2] clk: tegra30: Add hda clock default rates to clock
 driver
On 1/8/2021 7:29 PM, Peter Geis wrote:
> External email: Use caution opening links or attachments
>
>
> Current implementation defaults the hda clocks to clk_m. This causes hda
> to run too slow to operate correctly. Fix this by defaulting to pll_p and
> setting the frequency to the correct rate.
>
> This matches upstream t124 and downstream t30.
>
> Acked-by: Jon Hunter <jonathanh@...dia.com>
> Tested-by: Ion Agorria <ion@...rria.com>
> Signed-off-by: Peter Geis <pgwipeout@...il.com>
> ---
>   drivers/clk/tegra/clk-tegra30.c | 2 ++
>   1 file changed, 2 insertions(+)
Acked-by: Sameer Pujar <spujar@...dia.com>
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