lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Mon, 11 Jan 2021 10:16:59 -0800 (PST) From: matthew.gerlach@...ux.intel.com To: Moritz Fischer <mdf@...nel.org> cc: Lukas Bulwahn <lukas.bulwahn@...il.com>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Wu Hao <hao.wu@...el.com>, linux-fpga@...r.kernel.org, Tom Rix <trix@...hat.com>, linux-doc@...r.kernel.org, kernel-janitors@...r.kernel.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH -next] fpga: dfl-pci: rectify ReST formatting On Mon, 11 Jan 2021, Moritz Fischer wrote: > Hi Lukas, > > On Mon, Jan 11, 2021 at 12:21:13PM +0100, Lukas Bulwahn wrote: >> Commit fa41d10589be ("fpga: dfl-pci: locate DFLs by PCIe vendor specific >> capability") provides documentation to the FPGA Device Feature List (DFL) > Nit: Do you want to make this a Fixes: tag instead? >> Framework Overview, but introduced new documentation warnings: >> >> ./Documentation/fpga/dfl.rst: >> 505: WARNING: Title underline too short. >> 523: WARNING: Unexpected indentation. >> 523: WARNING: Blank line required after table. >> 524: WARNING: Block quote ends without a blank line; unexpected unindent. >> >> Rectify ReST formatting in ./Documentation/fpga/dfl.rst. >> >> Signed-off-by: Lukas Bulwahn <lukas.bulwahn@...il.com> > Acked-by: Moritz Fischer <mdf@...nel.org> Acked-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com> >> --- >> applies cleanly on next-20210111 >> >> Moritz, Matthew, please ack. >> >> Greg, please pick this doc fixup to your fpga -next tree on top of >> the commit above. >> >> Documentation/fpga/dfl.rst | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst >> index ea8cefc18bdb..c41ac76ffaae 100644 >> --- a/Documentation/fpga/dfl.rst >> +++ b/Documentation/fpga/dfl.rst >> @@ -502,7 +502,7 @@ FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) >> could be a reference. >> >> Location of DFLs on a PCI Device >> -=========================== >> +================================ >> The original method for finding a DFL on a PCI device assumed the start of the >> first DFL to offset 0 of bar 0. If the first node of the DFL is an FME, >> then further DFLs in the port(s) are specified in FME header registers. >> @@ -514,6 +514,7 @@ data begins with a 4 byte vendor specific register for the number of DFLs follow >> Offset/BIR vendor specific registers for each DFL. Bits 2:0 of Offset/BIR register >> indicates the BAR, and bits 31:3 form the 8 byte aligned offset where bits 2:0 are >> zero. >> +:: >> >> +----------------------------+ >> |31 Number of DFLS 0| >> -- >> 2.17.1 >> > > Thanks for doing this, I was about to send that same patch myself. > > - Moritz >
Powered by blists - more mailing lists