linux-kernel - [PATCH] mmc: sdhci-pci-gli: Finetune HS400 RX delay for GL9763E

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Message-Id: <20210111082249.17092-1-reniuschengl@gmail.com>
Date:   Mon, 11 Jan 2021 16:22:49 +0800
From:   Renius Chen <reniuschengl@...il.com>
To:     ulf.hansson@...aro.org, adrian.hunter@...el.com
Cc:     linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        ben.chuang@...esyslogic.com.tw, greg.tu@...esyslogic.com.tw,
        Renius Chen <reniuschengl@...il.com>
Subject: [PATCH] mmc: sdhci-pci-gli: Finetune HS400 RX delay for GL9763E

To improve the compatibility of GL9763E with HS400 eMMC cards,
finetune the RX delay of HS400 mode.

Signed-off-by: Renius Chen <reniuschengl@...il.com>
---
 drivers/mmc/host/sdhci-pci-gli.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 2d13bfcbcacf..14d9154f3af1 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -95,6 +95,10 @@
 #define PCIE_GLI_9763E_MMC_CTRL  0x960
 #define   GLI_9763E_HS400_SLOW     BIT(3)
 
+#define PCIE_GLI_9763E_CLKRXDLY  0x934
+#define   GLI_9763E_HS400_RXDLY    GENMASK(31, 28)
+#define   GLI_9763E_HS400_RXDLY_5  0x5
+
 #define SDHCI_GLI_9763E_CQE_BASE_ADDR	 0x200
 #define GLI_9763E_CQE_TRNS_MODE	   (SDHCI_TRNS_MULTI | \
 				    SDHCI_TRNS_BLK_CNT_EN | \
@@ -801,6 +805,11 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
 	value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MAX);
 	pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
 
+	pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
+	value &= ~GLI_9763E_HS400_RXDLY;
+	value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
+	pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
+
 	pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
 	value &= ~GLI_9763E_VHS_REV;
 	value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
-- 
2.27.0