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Message-ID: <20210111084748.GI3241@leoy-ThinkPad-X240s>
Date: Mon, 11 Jan 2021 16:47:48 +0800
From: Leo Yan <leo.yan@...aro.org>
To: Namhyung Kim <namhyung@...nel.org>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>,
Jiri Olsa <jolsa@...hat.com>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Andi Kleen <ak@...ux.intel.com>,
Ian Rogers <irogers@...gle.com>,
Kan Liang <kan.liang@...ux.intel.com>,
Joe Mario <jmario@...hat.com>, David Ahern <dsahern@...il.com>,
Don Zickus <dzickus@...hat.com>, Al Grant <Al.Grant@....com>,
James Clark <james.clark@....com>,
linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 10/11] perf c2c: Sort on all cache hit for load
operations
On Wed, Jan 06, 2021 at 04:52:15PM +0900, Namhyung Kim wrote:
[...]
> > @@ -2502,12 +2528,21 @@ static void print_pareto(FILE *out)
> > int ret;
> > const char *cl_output;
> >
> > - cl_output = "cl_num,"
> > - "cl_rmt_hitm,"
> > - "cl_lcl_hitm,"
> > - "cl_stores_l1hit,"
> > - "cl_stores_l1miss,"
> > - "dcacheline";
> > + if (c2c.display == DISPLAY_TOT || c2c.display == DISPLAY_LCL ||
> > + c2c.display == DISPLAY_RMT)
> > + cl_output = "cl_num,"
> > + "cl_rmt_hitm,"
> > + "cl_lcl_hitm,"
> > + "cl_stores_l1hit,"
> > + "cl_stores_l1miss,"
> > + "dcacheline";
> > + else /* c2c.display == DISPLAY_ALL */
> > + cl_output = "cl_num,"
> > + "cl_tot_ld_hit,"
> > + "cl_tot_ld_miss,"
> > + "cl_stores_l1hit,"
> > + "cl_stores_l1miss,"
> > + "dcacheline";
>
> Nit: You can keep the default value as is, and add an if statement
> just for the DISPLAY_ALL.
Okay, this might be more friendly for review. Will change to this
way.
> >
> > perf_hpp_list__init(&hpp_list);
> > ret = hpp_list__parse(&hpp_list, cl_output, NULL);
> > @@ -2543,7 +2578,7 @@ static void print_c2c_info(FILE *out, struct perf_session *session)
> > fprintf(out, "%-36s: %s\n", first ? " Events" : "", evsel__name(evsel));
> > first = false;
> > }
> > - fprintf(out, " Cachelines sort on : %s HITMs\n",
> > + fprintf(out, " Cachelines sort on : %s\n",
> > display_str[c2c.display]);
> > fprintf(out, " Cacheline data grouping : %s\n", c2c.cl_sort);
> > }
> > @@ -2700,7 +2735,7 @@ static int perf_c2c_browser__title(struct hist_browser *browser,
> > {
> > scnprintf(bf, size,
> > "Shared Data Cache Line Table "
> > - "(%lu entries, sorted on %s HITMs)",
> > + "(%lu entries, sorted on %s)",
> > browser->nr_non_filtered_entries,
> > display_str[c2c.display]);
> > return 0;
> > @@ -2906,6 +2941,8 @@ static int setup_display(const char *str)
> > c2c.display = DISPLAY_RMT;
> > else if (!strcmp(display, "lcl"))
> > c2c.display = DISPLAY_LCL;
> > + else if (!strcmp(display, "all"))
> > + c2c.display = DISPLAY_ALL;
> > else {
> > pr_err("failed: unknown display type: %s\n", str);
> > return -1;
> > @@ -2952,10 +2989,12 @@ static int build_cl_output(char *cl_sort, bool no_source)
> > }
> >
> > if (asprintf(&c2c.cl_output,
> > - "%s%s%s%s%s%s%s%s%s%s",
> > + "%s%s%s%s%s%s%s%s%s%s%s",
> > c2c.use_stdio ? "cl_num_empty," : "",
> > - "percent_rmt_hitm,"
> > - "percent_lcl_hitm,"
> > + c2c.display == DISPLAY_ALL ? "percent_ld_hit,"
> > + "percent_ld_miss," :
> > + "percent_rmt_hitm,"
> > + "percent_lcl_hitm,",
> > "percent_stores_l1hit,"
> > "percent_stores_l1miss,"
> > "offset,offset_node,dcacheline_count,",
> > @@ -2984,6 +3023,7 @@ static int build_cl_output(char *cl_sort, bool no_source)
> > static int setup_coalesce(const char *coalesce, bool no_source)
> > {
> > const char *c = coalesce ?: coalesce_default;
> > + const char *sort_str = NULL;
> >
> > if (asprintf(&c2c.cl_sort, "offset,%s", c) < 0)
> > return -ENOMEM;
> > @@ -2991,12 +3031,16 @@ static int setup_coalesce(const char *coalesce, bool no_source)
> > if (build_cl_output(c2c.cl_sort, no_source))
> > return -1;
> >
> > - if (asprintf(&c2c.cl_resort, "offset,%s",
> > - c2c.display == DISPLAY_TOT ?
> > - "tot_hitm" :
> > - c2c.display == DISPLAY_RMT ?
> > - "rmt_hitm,lcl_hitm" :
> > - "lcl_hitm,rmt_hitm") < 0)
> > + if (c2c.display == DISPLAY_TOT)
> > + sort_str = "tot_hitm";
> > + else if (c2c.display == DISPLAY_RMT)
> > + sort_str = "rmt_hitm,lcl_hitm";
> > + else if (c2c.display == DISPLAY_LCL)
> > + sort_str = "lcl_hitm,rmt_hitm";
> > + else if (c2c.display == DISPLAY_ALL)
> > + sort_str = "tot_ld_hit";
> > +
> > + if (asprintf(&c2c.cl_resort, "offset,%s", sort_str) < 0)
> > return -ENOMEM;
> >
> > pr_debug("coalesce sort fields: %s\n", c2c.cl_sort);
> > @@ -3131,20 +3175,37 @@ static int perf_c2c__report(int argc, const char **argv)
> > goto out_mem2node;
> > }
> >
> > - output_str = "cl_idx,"
> > - "dcacheline,"
> > - "dcacheline_node,"
> > - "dcacheline_count,"
> > - "percent_hitm,"
> > - "tot_hitm,lcl_hitm,rmt_hitm,"
> > - "tot_recs,"
> > - "tot_loads,"
> > - "tot_stores,"
> > - "stores_l1hit,stores_l1miss,"
> > - "ld_fbhit,ld_l1hit,ld_l2hit,"
> > - "ld_lclhit,lcl_hitm,"
> > - "ld_rmthit,rmt_hitm,"
> > - "dram_lcl,dram_rmt";
> > + if (c2c.display == DISPLAY_TOT || c2c.display == DISPLAY_LCL ||
> > + c2c.display == DISPLAY_RMT)
> > + output_str = "cl_idx,"
> > + "dcacheline,"
> > + "dcacheline_node,"
> > + "dcacheline_count,"
> > + "percent_hitm,"
> > + "tot_hitm,lcl_hitm,rmt_hitm,"
> > + "tot_recs,"
> > + "tot_loads,"
> > + "tot_stores,"
> > + "stores_l1hit,stores_l1miss,"
> > + "ld_fbhit,ld_l1hit,ld_l2hit,"
> > + "ld_lclhit,lcl_hitm,"
> > + "ld_rmthit,rmt_hitm,"
> > + "dram_lcl,dram_rmt";
> > + else /* c2c.display == DISPLAY_ALL */
> > + output_str = "cl_idx,"
> > + "dcacheline,"
> > + "dcacheline_node,"
> > + "dcacheline_count,"
> > + "percent_tot_ld_hit,"
> > + "tot_ld_hit,"
> > + "tot_recs,"
> > + "tot_loads,"
> > + "tot_stores,"
> > + "stores_l1hit,stores_l1miss,"
> > + "ld_fbhit,ld_l1hit,ld_l2hit,"
> > + "ld_lclhit,lcl_hitm,"
> > + "ld_rmthit,rmt_hitm,"
> > + "dram_lcl,dram_rmt";
>
> Ditto.
Agreed.
Thanks,
Leo
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