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Message-ID: <CAPDyKFrRKbQS1+t_nGH9RRKf0WGcAf-Pjzo1rJt=Sz=SMWOa7Q@mail.gmail.com>
Date: Tue, 12 Jan 2021 14:57:41 +0100
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Dmitry Osipenko <digetx@...il.com>
Cc: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Mark Brown <broonie@...nel.org>,
Liam Girdwood <lgirdwood@...il.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Peter Geis <pgwipeout@...il.com>,
Nicolas Chauvet <kwizart@...il.com>,
Krzysztof Kozlowski <krzk@...nel.org>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Kevin Hilman <khilman@...nel.org>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Viresh Kumar <vireshk@...nel.org>,
Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
driverdevel <devel@...verdev.osuosl.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
DTML <devicetree@...r.kernel.org>,
dri-devel <dri-devel@...ts.freedesktop.org>,
Linux Media Mailing List <linux-media@...r.kernel.org>,
linux-tegra <linux-tegra@...r.kernel.org>,
linux-clk <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v2 31/48] soc/tegra: regulators: Support Core domain state syncing
On Thu, 17 Dec 2020 at 19:07, Dmitry Osipenko <digetx@...il.com> wrote:
>
> The core voltage shall not drop until state of Core domain is synced,
> i.e. all device drivers that use Core domain are loaded and ready.
>
> Support Core domain state syncing. The Core domain driver invokes the
> core-regulator voltage syncing once the state of domain is synced, at
> this point the Core voltage is allowed to go lower.
>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
This looks reasonable to me, feel free to add:
Reviewed-by: Ulf Hansson <ulf.hansson@...aro.org>
Kind regards
Uffe
> ---
> drivers/soc/tegra/regulators-tegra20.c | 19 ++++++++++++++++++-
> drivers/soc/tegra/regulators-tegra30.c | 18 +++++++++++++++++-
> 2 files changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/tegra/regulators-tegra20.c b/drivers/soc/tegra/regulators-tegra20.c
> index 367a71a3cd10..e2c11d442591 100644
> --- a/drivers/soc/tegra/regulators-tegra20.c
> +++ b/drivers/soc/tegra/regulators-tegra20.c
> @@ -16,6 +16,8 @@
> #include <linux/regulator/driver.h>
> #include <linux/regulator/machine.h>
>
> +#include <soc/tegra/common.h>
> +
> struct tegra_regulator_coupler {
> struct regulator_coupler coupler;
> struct regulator_dev *core_rdev;
> @@ -38,6 +40,21 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra,
> int core_cur_uV;
> int err;
>
> + /*
> + * Tegra20 SoC has critical DVFS-capable devices that are
> + * permanently-active or active at a boot time, like EMC
> + * (DRAM controller) or Display controller for example.
> + *
> + * The voltage of a CORE SoC power domain shall not be dropped below
> + * a minimum level, which is determined by device's clock rate.
> + * This means that we can't fully allow CORE voltage scaling until
> + * the state of all DVFS-critical CORE devices is synced.
> + */
> + if (tegra_soc_core_domain_state_synced()) {
> + pr_info_once("voltage state synced\n");
> + return 0;
> + }
> +
> if (tegra->core_min_uV > 0)
> return tegra->core_min_uV;
>
> @@ -58,7 +75,7 @@ static int tegra20_core_limit(struct tegra_regulator_coupler *tegra,
> */
> tegra->core_min_uV = core_max_uV;
>
> - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV);
> + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV);
>
> return tegra->core_min_uV;
> }
> diff --git a/drivers/soc/tegra/regulators-tegra30.c b/drivers/soc/tegra/regulators-tegra30.c
> index 0e776b20f625..42d675b79fa3 100644
> --- a/drivers/soc/tegra/regulators-tegra30.c
> +++ b/drivers/soc/tegra/regulators-tegra30.c
> @@ -16,6 +16,7 @@
> #include <linux/regulator/driver.h>
> #include <linux/regulator/machine.h>
>
> +#include <soc/tegra/common.h>
> #include <soc/tegra/fuse.h>
>
> struct tegra_regulator_coupler {
> @@ -39,6 +40,21 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra,
> int core_cur_uV;
> int err;
>
> + /*
> + * Tegra30 SoC has critical DVFS-capable devices that are
> + * permanently-active or active at a boot time, like EMC
> + * (DRAM controller) or Display controller for example.
> + *
> + * The voltage of a CORE SoC power domain shall not be dropped below
> + * a minimum level, which is determined by device's clock rate.
> + * This means that we can't fully allow CORE voltage scaling until
> + * the state of all DVFS-critical CORE devices is synced.
> + */
> + if (tegra_soc_core_domain_state_synced()) {
> + pr_info_once("voltage state synced\n");
> + return 0;
> + }
> +
> if (tegra->core_min_uV > 0)
> return tegra->core_min_uV;
>
> @@ -59,7 +75,7 @@ static int tegra30_core_limit(struct tegra_regulator_coupler *tegra,
> */
> tegra->core_min_uV = core_max_uV;
>
> - pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV);
> + pr_info("core voltage initialized to %duV\n", tegra->core_min_uV);
>
> return tegra->core_min_uV;
> }
> --
> 2.29.2
>
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