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Date: Tue, 12 Jan 2021 16:34:19 +0100 From: Bjarni Jonasson <bjarni.jonasson@...rochip.com> To: Michał Mirosław <mirqus@...il.com> CC: Russell King <linux@...linux.org.uk>, Andrew Lunn <andrew@...n.ch>, "Heiner Kallweit" <hkallweit1@...il.com>, "David S. Miller" <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>, netdev <netdev@...r.kernel.org>, "Linux Kernel" <linux-kernel@...r.kernel.org>, UNGLinuxDriver <UNGLinuxDriver@...rochip.com> Subject: Re: [PATCH v1 1/2] net: phy: Add 100 base-x mode On Mon, 2021-01-11 at 20:37 +0100, Michał Mirosław wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > pon., 11 sty 2021 o 14:54 Bjarni Jonasson > <bjarni.jonasson@...rochip.com> napisał(a): > > Sparx-5 supports this mode and it is missing in the PHY core. > > > > Signed-off-by: Bjarni Jonasson <bjarni.jonasson@...rochip.com> > > --- > > include/linux/phy.h | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/include/linux/phy.h b/include/linux/phy.h > > index 56563e5e0dc7..dce867222d58 100644 > > --- a/include/linux/phy.h > > +++ b/include/linux/phy.h > > @@ -111,6 +111,7 @@ extern const int phy_10gbit_features_array[1]; > > * @PHY_INTERFACE_MODE_10GBASER: 10G BaseR > > * @PHY_INTERFACE_MODE_USXGMII: Universal Serial 10GE MII > > * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN > > + * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX > > * @PHY_INTERFACE_MODE_MAX: Book keeping > > [...] > > This is kernel-internal interface, so maybe the new mode can be > inserted before 1000baseX for easier lookup? > > Best Regards > Michał Mirosław Yes, will do that. -- Bjarni Jonasson Microchip
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