lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Tue, 12 Jan 2021 08:56:44 -0800
From:   Sowjanya Komatineni <skomatineni@...dia.com>
To:     David Laight <David.Laight@...LAB.COM>,
        Dmitry Osipenko <digetx@...il.com>,
        Thierry Reding <thierry.reding@...il.com>
CC:     "jonathanh@...dia.com" <jonathanh@...dia.com>,
        "linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-i2c@...r.kernel.org" <linux-i2c@...r.kernel.org>
Subject: Re: [PATCH v1] i2c: tegra: Fix i2c_writesl() to use writel() instead
 of writesl()


On 1/12/21 1:32 AM, David Laight wrote:
> From: Sowjanya Komatineni
>> Sent: 11 January 2021 17:38
> ...
>> Using writesl() for filling TX_FIFO causing silent hang immediate on any
>> i2c register access after filling FIFO with 8 words and some times with
>> 6 words as well.
>>
>> So couldn't INTERRUPT_STATUS registers to check for TX FIFO Overflows
>> when this silent hang happens.
>>
>> Tried to read thru back-door (JTAG path) but could not connect to JTAG
>> either. Looks like Tegra chip is in some weird state.
>>
>> But using writel() followed by i2c_readl helps. Not sure if any thing
>> related to register access delay or some other issue.
> How much does the i2c_read() slow down the transfer?
> If the device is PCIe it is probably significant.
>
> If the underlying problem is that the Tegra chip can't handle
> back to back writes to the tx fifo maybe there are other solutions!
> 1) Send it back and ask for a working chip :-)
> 2) Maybe an interleaved write will slow things down enough?
>
> It may be worth testing back to back writes to other registers
> to see if it is a problem that is specific to the tx fifo.
>
> 	David
>
> -
> Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
> Registration No: 1397386 (Wales)

This is a known hardware bug with VI I2C controller which is under 
host1x where immediate multiple writes to TX FIFO register gets stuck 
and reading from a register allows them to be flushed out.

VI I2C is dedicated for camera sensors or HDMI2CSI bridge.

Powered by blists - more mailing lists