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Date: Tue, 12 Jan 2021 19:20:52 +0100
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>
To: linux-arm-msm@...r.kernel.org
Cc: konrad.dybcio@...ainline.org, marijn.suijten@...ainline.org,
martin.botka@...ainline.org, phone-devel@...r.kernel.org,
linux-kernel@...r.kernel.org, robh+dt@...nel.org,
rjw@...ysocki.net, viresh.kumar@...aro.org, nks@...wful.org,
agross@...nel.org, bjorn.andersson@...aro.org,
daniel.lezcano@...aro.org, manivannan.sadhasivam@...aro.org,
devicetree@...r.kernel.org, linux-pm@...r.kernel.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@...ainline.org>
Subject: [PATCH v3 15/15] dt-bindings: cpufreq: qcom-hw: Add bindings for 8998
The OSM programming addition has been done under the
qcom,cpufreq-hw-8998 compatible name: specify the requirement
of two additional register spaces for this functionality.
This implementation, with the same compatible, has been
tested on MSM8998 and SDM630.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
---
.../bindings/cpufreq/cpufreq-qcom-hw.yaml | 66 +++++++++++++++----
1 file changed, 52 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
index bc81b6203e27..17fd6a6cefb0 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -18,6 +18,10 @@ description: |
properties:
compatible:
oneOf:
+ - description: Non-secure v1 of CPUFREQ HW
+ items:
+ - const: qcom,cpufreq-hw-8998
+
- description: v1 of CPUFREQ HW
items:
- const: qcom,cpufreq-hw
@@ -28,21 +32,9 @@ properties:
- qcom,sm8250-cpufreq-epss
- const: qcom,cpufreq-epss
- reg:
- minItems: 2
- maxItems: 3
- items:
- - description: Frequency domain 0 register region
- - description: Frequency domain 1 register region
- - description: Frequency domain 2 register region
+ reg: {}
- reg-names:
- minItems: 2
- maxItems: 3
- items:
- - const: freq-domain0
- - const: freq-domain1
- - const: freq-domain2
+ reg-names: {}
clocks:
items:
@@ -57,6 +49,52 @@ properties:
'#freq-domain-cells':
const: 1
+if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,cpufreq-hw-8998
+then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 6
+ items:
+ - description: Frequency domain 0 register region
+ - description: Operating State Manager domain 0 register region
+ - description: Frequency domain 1 register region
+ - description: Operating State Manager domain 1 register region
+ - description: PLL ACD domain 0 register region (if ACD programming required)
+ - description: PLL ACD domain 1 register region (if ACD programming required)
+
+ reg-names:
+ minItems: 2
+ maxItems: 6
+ items:
+ - const: "osm-domain0"
+ - const: "freq-domain0"
+ - const: "osm-domain1"
+ - const: "freq-domain1"
+ - const: "osm-acd0"
+ - const: "osm-acd1"
+
+else:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 3
+ items:
+ - description: Frequency domain 0 register region
+ - description: Frequency domain 1 register region
+ - description: Frequency domain 2 register region
+ reg-names:
+ minItems: 2
+ maxItems: 3
+ items:
+ - const: "freq-domain0"
+ - const: "freq-domain1"
+ - const: "freq-domain2"
+
required:
- compatible
- reg
--
2.29.2
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