| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <161048188125.3661239.13161942092910464158@swboyd.mtv.corp.google.com>
Date: Tue, 12 Jan 2021 12:04:41 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Michael Turquette <mturquette@...libre.com>,
Taniya Das <tdas@...eaurora.org>
Cc: Rajendra Nayak <rnayak@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, robh@...nel.org, robh+dt@...nel.org,
Taniya Das <tdas@...eaurora.org>
Subject: Re: [PATCH v1 2/2] clk: qcom: Add Global Clock controller (GCC) driver for SC7280
Quoting Taniya Das (2020-12-15 10:48:34)
> diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
> new file mode 100644
> index 0000000..74a3151
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-sc7280.c
> @@ -0,0 +1,3361 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +
> +#include <dt-bindings/clock/qcom,gcc-sc7280.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "common.h"
> +#include "gdsc.h"
> +#include "reset.h"
> +
[...]
> +static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
> + F(144000, P_BI_TCXO, 16, 3, 25),
> + F(400000, P_BI_TCXO, 12, 1, 4),
> + F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> + F(192000000, P_GCC_GPLL10_OUT_MAIN, 2, 0, 0),
> + F(384000000, P_GCC_GPLL10_OUT_MAIN, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
> + .cmd_rcgr = 0x7500c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_8,
> + .freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc1_apps_clk_src",
> + .parent_data = gcc_parent_data_8,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_8),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
This needs to use floor clk ops?
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> + F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
> + F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
> + .cmd_rcgr = 0x7502c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_1,
> + .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc1_ice_core_clk_src",
> + .parent_data = gcc_parent_data_1,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
Same.
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
> + F(400000, P_BI_TCXO, 12, 1, 4),
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> + F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
> + .cmd_rcgr = 0x1400c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_9,
> + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc2_apps_clk_src",
> + .parent_data = gcc_parent_data_9,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_9),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
Same.
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
> + F(400000, P_BI_TCXO, 12, 1, 4),
> + F(19200000, P_BI_TCXO, 1, 0, 0),
> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
> + .cmd_rcgr = 0x1600c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_1,
> + .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc4_apps_clk_src",
> + .parent_data = gcc_parent_data_1,
> + .num_parents = ARRAY_SIZE(gcc_parent_data_1),
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_rcg2_ops,
Same.
> + },
> +};
> +
[...]
> +static struct clk_branch gcc_cpuss_ahb_clk = {
> + .halt_reg = 0x48000,
> + .halt_check = BRANCH_HALT_VOTED,
> + .hwcg_reg = 0x48000,
> + .hwcg_bit = 1,
> + .clkr = {
> + .enable_reg = 0x52000,
> + .enable_mask = BIT(21),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_cpuss_ahb_clk",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
> + },
> + .num_parents = 1,
> + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
Why is it critical? Please add a comment like sc7180.
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
Powered by blists - more mailing lists