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Date:   Tue, 12 Jan 2021 20:35:50 +0800
From:   "Leizhen (ThunderTown)" <>
To:     Arnd Bergmann <>
CC:     Russell King <>,
        Greg Kroah-Hartman <>,
        Will Deacon <>,
        "Haojian Zhuang" <>,
        Arnd Bergmann <>,
        Rob Herring <>,
        Wei Xu <>,
        devicetree <>,
        linux-arm-kernel <>,
        linux-kernel <>
Subject: Re: [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3
 cache controller

On 2021/1/12 16:46, Arnd Bergmann wrote:
> On Tue, Jan 12, 2021 at 2:56 AM Zhen Lei <> wrote:
>> +---
>> +$id:
>> +$schema:
>> +
>> +title: Hisilicon L3 cache controller
>> +
>> +maintainers:
>> +  - Wei Xu <>
>> +
>> +description: |
>> +  The Hisilicon L3 outer cache controller supports a maximum of 36-bit physical
>> +  addresses. The data cached in the L3 outer cache can be operated based on the
>> +  physical address range or the entire cache.
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - const: hisilicon,l3cache
>> +
> The compatible string needs to be a little more specific, I'm sure
> you cannot guarantee that this is the only L3 cache controller ever
> designed in the past or future by HiSilicon.
> Normally when you have an IP block that is itself unnamed but that is specific
> to one or a few SoCs but that has no na, the convention is to include the name
> of the first SoC that contained it.

Right, thanks for your suggestion, I will rename it to "hisilicon,hi1381-l3cache"
and "hisilicon,hi1215-l3cache".

> Can you share which products actually use this L3 cache controller?

This L3 cache controller is used on Hi1381 and Hi1215 board. I don't know where
these two boards are used. Our company is too large. Software is delivered level
by level. I'm only involved in the Kernel-related part.

> On a related note, what does the memory map look like on this chip?

memory@...000 {
     device_type = "memory";
     reg = <0x0 0xa00000 0x0 0x1aa00000>, <0x1 0xe0000000 0x0 0x1d000000>, <0x0 0x1f400000 0x0 0xb5c00000>;

Currently, the DTS is being maintained by ourselves, I'll try to upstream it later.

> Do you support more than 4GB of total installed memory? If you

Currently, the total size does not exceed 4 GB. However, the physical address is wider than 32 bits.

> do, this becomes a problem in the future as highmem support
> winds down. In fact  anything more than 1GB on a 32-bit system
> requires more work on the kernel to be completed before we remove
> highmem, and will incur a slowdown. If the total is under 4GB but the
> memory is not in a contiguous physical address range. See my
> Linaro connect presentation[1] for further information on the topic.


>        Arnd
> [1]
> .

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