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Date:   Wed, 13 Jan 2021 16:09:17 +0000
From:   Mark Brown <broonie@...nel.org>
To:     Rob Herring <robh@...nel.org>
Cc:     Richard Fitzgerald <rf@...nsource.cirrus.com>,
        kuninori.morimoto.gx@...esas.com, nsaenzjulienne@...e.de,
        f.fainelli@...il.com, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, alsa-devel@...a-project.org,
        patches@...nsource.cirrus.com,
        bcm-kernel-feedback-list@...adcom.com,
        linux-rpi-kernel@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v4 2/6] dt-bindings: audio-graph-card: Add plls and
 sysclks properties

On Wed, Jan 13, 2021 at 09:22:25AM -0600, Rob Herring wrote:

> I'm not sure this makes sense to be generic, but if so, we already have 
> the clock binding and should use (and possibly extend) that.

> This appears to all be configuration of clocks within the codec, so 
> these properties belong in the codec or cpu nodes.

Right, I think this should just be the clock binding. 

> > +      The PLL id and clock source id are specific to the particular component
> > +      so see the relevant component driver for the ids. Typically the

This should refer to the bindings for components, not to their drivers.

> > +      clock source id indicates the pin the source clock is connected to.
> > +      The same phandle can appear in multiple entries so that several plls
> > +      can be set in the same component.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +
> > +  plls-clocks:
> > +    $ref: /schemas/types.yaml#/definitions/non-unique-string-array
> > +    description: |
> > +      A list of clock names giving the source clock for each setting
> > +      in the plls property.
> > +
> > +  sysclks:
> > +    description: |
> > +      A list of component sysclk settings. There are 4 cells per sysclk
> > +      setting:
> > +        - phandle to the node of the codec or cpu component,
> > +        - component sysclk id,
> > +        - component clock source id,
> > +        - direction of the clock: 0 if the clock is an input to the component,
> > +          1 if it is an output.
> 
> A clock provider and consumer would provide the direction.
> 
> > +      The sysclk id and clock source id are specific to the particular
> > +      component so see the relevant component driver for the ids. Typically
> > +      the clock source id indicates the pin the source clock is connected to.
> > +      The same phandle can appear in multiple entries so that several sysclks
> > +      can be set in the same component.
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +
> > +  sysclks-clocks:
> > +    $ref: /schemas/types.yaml#/definitions/non-unique-string-array
> > +    description: |
> > +      A list of clock names giving the source clock for each setting
> > +      in the sysclks property.
> > +
> > +dependencies:
> > +  plls: [ plls-clocks ]
> > +  sysclks: [ sysclks-clocks ]
> > +
> >  required:
> >    - dais
> >  
> > -- 
> > 2.20.1
> > 

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