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Message-ID: <20210113033154.GA1480568@robh.at.kernel.org>
Date:   Tue, 12 Jan 2021 21:31:54 -0600
From:   Rob Herring <robh@...nel.org>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc:     sboyd@...nel.org, linux-arm-msm@...r.kernel.org,
        viresh.kumar@...aro.org, mturquette@...libre.com,
        jassisinghbrar@...il.com, robh+dt@...nel.org,
        bjorn.andersson@...aro.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, ulf.hansson@...aro.org,
        devicetree@...r.kernel.org, agross@...nel.org
Subject: Re: [PATCH v2 3/5] dt-bindings: clock: Add Qualcomm A7 PLL binding

On Fri, 08 Jan 2021 17:02:31 +0530, Manivannan Sadhasivam wrote:
> Add devicetree YAML binding for Cortex A7 PLL clock in Qualcomm
> platforms like SDX55.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> ---
>  .../devicetree/bindings/clock/qcom,a7pll.yaml | 51 +++++++++++++++++++
>  1 file changed, 51 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> 

Reviewed-by: Rob Herring <robh@...nel.org>

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