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Message-ID: <CAPDyKFo=GE2GNuv0=SXfuSSgE-b0iBhXCxqvd=cgspqX6hph2w@mail.gmail.com>
Date: Wed, 13 Jan 2021 12:25:20 +0100
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Renius Chen <reniuschengl@...il.com>
Cc: Adrian Hunter <adrian.hunter@...el.com>,
"linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Ben Chuang <ben.chuang@...esyslogic.com.tw>,
greg.tu@...esyslogic.com.tw
Subject: Re: [PATCH] mmc: sdhci-pci-gli: Add a switch to enable/disable CQHCI support
On Wed, 6 Jan 2021 at 09:53, Renius Chen <reniuschengl@...il.com> wrote:
>
> Add a vendor-specific bit named GLI_9763E_MB_ERP_ON at the bit7 of
> register 888h to decide whether to enhance random R/W performance
> of GL9763E. CQHCI support will be enabled if and only if the bit is
> set and the GLI_9763E_MB_CMQ_OFF bit is not set.
>
> Signed-off-by: Renius Chen <reniuschengl@...il.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-pci-gli.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index b85edd62e7f0..c6a107d7c742 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -84,6 +84,7 @@
> #define GLI_9763E_VHS_REV_W 0x2
> #define PCIE_GLI_9763E_MB 0x888
> #define GLI_9763E_MB_CMDQ_OFF BIT(19)
> +#define GLI_9763E_MB_ERP_ON BIT(7)
> #define PCIE_GLI_9763E_SCR 0x8E0
> #define GLI_9763E_SCR_AXI_REQ BIT(9)
>
> @@ -814,7 +815,8 @@ static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
>
> pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
> if (!(value & GLI_9763E_MB_CMDQ_OFF))
> - host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
> + if (value & GLI_9763E_MB_ERP_ON)
> + host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
>
> gli_pcie_enable_msi(slot);
> host->mmc_host_ops.hs400_enhanced_strobe =
> --
> 2.27.0
>
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