linux-kernel - [PATCH v2 1/2] rtc: pcf2127: Disable Power-On Reset Override

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Date:   Wed, 13 Jan 2021 12:27:41 +0100
From:   Philipp Rosenberger <p.rosenberger@...bus.com>
To:     unlisted-recipients:; (no To-header on input)
Cc:     p.rosenberger@...bus.com, dan.carpenter@...cle.com,
        u.kleine-koenig@...gutronix.de, biwen.li@....com, lvb@...hos.com,
        bruno.thomsen@...il.com, l.sanfilippo@...bus.com,
        Alessandro Zummo <a.zummo@...ertech.it>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        linux-rtc@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH v2 1/2] rtc: pcf2127: Disable Power-On Reset Override

To resume normal operation after a total power loss (no or empty
battery) the "Power-On Reset Override (PORO)" facility needs to be
disabled.

As the oscillator may take a long time (200 ms to 2 s) to resume normal
operation. The default behaviour is to use the PORO facility. But with
the PORO active no interrupts are generated on the interrupt pin (INT).

Signed-off-by: Philipp Rosenberger <p.rosenberger@...bus.com>
---
 drivers/rtc/rtc-pcf2127.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 39a7b5116aa4..378b1ce812d6 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -26,6 +26,7 @@
 
 /* Control register 1 */
 #define PCF2127_REG_CTRL1		0x00
+#define PCF2127_BIT_CTRL1_POR_OVRD		BIT(3)
 #define PCF2127_BIT_CTRL1_TSF1			BIT(4)
 /* Control register 2 */
 #define PCF2127_REG_CTRL2		0x01
@@ -612,6 +613,23 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap,
 		ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
 	}
 
+	/*
+	 * The "Power-On Reset Override" facility prevents the RTC to do a reset
+	 * after power on. For normal operation the PORO must be disabled.
+	 */
+	regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
+				PCF2127_BIT_CTRL1_POR_OVRD);
+	/*
+	 * If the PORO can't be disabled, just move on. The RTC should
+	 * work fine, but functions like watchdog and alarm interrupts might
+	 * not work. There will be no interrupt generated on the interrupt pin.
+	 */
+	ret = regmap_test_bits(pcf2127->regmap, PCF2127_REG_CTRL1, PCF2127_BIT_CTRL1_POR_OVRD);
+	if (ret <= 0) {
+		dev_err(dev, "%s: can't disable PORO (ctrl1).\n", __func__);
+		dev_warn(dev, "Watchdog and alarm functions might not work properly\n");
+	}
+
 	/*
 	 * Watchdog timer enabled and reset pin /RST activated when timed out.
 	 * Select 1Hz clock source for watchdog timer.
-- 
2.29.2