linux-kernel - Re: [PATCH 1/3] phy: qcom-qusb2: Allow specifying default clock scheme

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Message-ID: <28bb9e1e-909a-1559-af62-bc99b6e960ec@somainline.org>
Date:   Thu, 14 Jan 2021 18:57:44 +0100
From:   AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@...ainline.org>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>
Cc:     agross@...nel.org, kishon@...com, vkoul@...nel.org,
        robh+dt@...nel.org, mgautam@...eaurora.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, konrad.dybcio@...ainline.org,
        martin.botka@...ainline.org, marijn.suijten@...ainline.org,
        phone-devel@...r.kernel.org
Subject: Re: [PATCH 1/3] phy: qcom-qusb2: Allow specifying default clock
 scheme

Il 14/01/21 18:52, Bjorn Andersson ha scritto:
> On Thu 14 Jan 11:47 CST 2021, AngeloGioacchino Del Regno wrote:
> 
>> The TCSR's PHY_CLK_SCHEME register is not available on all SoC
>> models, but some may still use a differential reference clock.
>>
>> In preparation for these SoCs, add a se_clk_scheme_default
>> configuration entry and declare it to true for all currently
>> supported SoCs (retaining the previous defaults.
>>
>> This patch brings no functional changes.
>>
> 
> Reviewed-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> 

Thanks!! :)

>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...ainline.org>
>> ---
>>   drivers/phy/qualcomm/phy-qcom-qusb2.c | 15 +++++++++++++--
>>   1 file changed, 13 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> index 109792203baf..8fcfea2a8f1f 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
>> @@ -245,6 +245,9 @@ struct qusb2_phy_cfg {
>>   
>>   	/* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
>>   	bool has_pll_override;
>> +
>> +	/* true if PHY default clk scheme is single-ended */
>> +	bool se_clk_scheme_default;
>>   };
>>   
>>   static const struct qusb2_phy_cfg msm8996_phy_cfg = {
>> @@ -253,6 +256,7 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
>>   	.regs		= msm8996_regs_layout,
>>   
>>   	.has_pll_test	= true,
>> +	.se_clk_scheme_default = true,
>>   	.disable_ctrl	= (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
>>   	.mask_core_ready = PLL_LOCKED,
>>   	.autoresume_en	 = BIT(3),
>> @@ -266,6 +270,7 @@ static const struct qusb2_phy_cfg msm8998_phy_cfg = {
>>   	.disable_ctrl   = POWER_DOWN,
>>   	.mask_core_ready = CORE_READY_STATUS,
>>   	.has_pll_override = true,
>> +	.se_clk_scheme_default = true,
>>   	.autoresume_en   = BIT(0),
>>   	.update_tune1_with_efuse = true,
>>   };
>> @@ -279,6 +284,7 @@ static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
>>   			   POWER_DOWN),
>>   	.mask_core_ready = CORE_READY_STATUS,
>>   	.has_pll_override = true,
>> +	.se_clk_scheme_default = true,
>>   	.autoresume_en	  = BIT(0),
>>   	.update_tune1_with_efuse = true,
>>   };
>> @@ -701,8 +707,13 @@ static int qusb2_phy_init(struct phy *phy)
>>   	/* Required to get phy pll lock successfully */
>>   	usleep_range(150, 160);
>>   
>> -	/* Default is single-ended clock on msm8996 */
>> -	qphy->has_se_clk_scheme = true;
>> +	/*
>> +	 * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME
>> +	 * register in the TCSR so, if there's none, use the default
>> +	 * value hardcoded in the configuration.
>> +	 */
>> +	qphy->has_se_clk_scheme = cfg->se_clk_scheme_default;
>> +
>>   	/*
>>   	 * read TCSR_PHY_CLK_SCHEME register to check if single-ended
>>   	 * clock scheme is selected. If yes, then disable differential
>> -- 
>> 2.29.2
>>