linux-kernel - Re: [PATCH] KVM: x86/pmu: Fix HW_REF_CPU_CYCLES event pseudo-encoding in intel_arch

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <YAHRMK5SmrmMx8hg@google.com>
Date:   Fri, 15 Jan 2021 09:30:24 -0800
From:   Sean Christopherson <seanjc@...gle.com>
To:     Like Xu <like.xu@...ux.intel.com>
Cc:     Paolo Bonzini <pbonzini@...hat.com>,
        Stephane Eranian <eranian@...gle.com>,
        Vitaly Kuznetsov <vkuznets@...hat.com>,
        Wanpeng Li <wanpengli@...cent.com>,
        Jim Mattson <jmattson@...gle.com>,
        Joerg Roedel <joro@...tes.org>, kvm@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] KVM: x86/pmu: Fix HW_REF_CPU_CYCLES event
 pseudo-encoding in intel_arch_events[]

On Fri, Jan 15, 2021, Like Xu wrote:
> Ping ?
> 
> On 2020/12/30 16:19, Like Xu wrote:
> > The HW_REF_CPU_CYCLES event on the fixed counter 2 is pseudo-encoded as
> > 0x0300 in the intel_perfmon_event_map[]. Correct its usage.
> > 
> > Fixes: 62079d8a4312 ("KVM: PMU: add proper support for fixed counter 2")
> > Signed-off-by: Like Xu <like.xu@...ux.intel.com>

Reviewed-by: Sean Christopherson <seanjc@...gle.com> 

> > ---
> >   arch/x86/kvm/vmx/pmu_intel.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> > index a886a47daebd..013e8d253dfa 100644
> > --- a/arch/x86/kvm/vmx/pmu_intel.c
> > +++ b/arch/x86/kvm/vmx/pmu_intel.c
> > @@ -29,7 +29,7 @@ static struct kvm_event_hw_type_mapping intel_arch_events[] = {
> >   	[4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES },
> >   	[5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
> >   	[6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
> > -	[7] = { 0x00, 0x30, PERF_COUNT_HW_REF_CPU_CYCLES },
> > +	[7] = { 0x00, 0x03, PERF_COUNT_HW_REF_CPU_CYCLES },

In a follow up patch, would it be sane/appropriate to define these magic numbers
in asm/perf_event.h and share them between intel_perfmon_event_map and
intel_arch_events?  Without this patch, it's not at all obvious that these are
intended to align with the Core (arch?) event definitions.

> >   };
> >   /* mapping between fixed pmc index and intel_arch_events array */
>